diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-07 17:07:26 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-25 11:03:49 +0000 |
| commit | 5d1f9a009647c741e8587015b14f1e852e1c489e (patch) | |
| tree | b6e87bac2f8a578b7bee6b73111e04bd3750eeb8 /src/southbridge/intel/bd82x6x | |
| parent | 2de19038beffa154eefe40755b607aa9f94d9f9f (diff) | |
Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)
This patch cleans up remaining uses of raw boolean Kconfig values I
could find by wrapping them with CONFIG(). The remaining naked config
value warnings in the code should all be false positives now (although
the process was semi-manual and involved some eyeballing so I may have
missed a few).
Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index eda16da6f7..e9e49649f2 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -418,7 +418,7 @@ static void enable_clock_gating(struct device *dev) static void pch_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { + if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode |