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authorDuncan Laurie <dlaurie@chromium.org>2012-06-23 17:25:29 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-26 20:28:38 +0200
commit0920915bca2391ed318eeb12ddad8b7cb4a52905 (patch)
tree25756ddcc76e563c636e3ba925c55177cfbb0c91 /src/southbridge/intel/bd82x6x/usb_ehci.c
parent38bd80d5a7320dc1b9277c00f18539cc4f878776 (diff)
ELOG: Support GSMI in CPT/PPT southbridge SMI handler
In order to support the GSMI interface the SMI handler needs to find and use the state save area from the same CPU that initiated the SMI. In this case it is a synchronous SMI resulting form an IO write to port 0xB2. To find the right CPU state save area iterate over the region until the "IO Misc Info" field reports the expected value and then proceed to use that state save area. This is needed because the coreboot SMI handler only executes on one core, and that core is non-deterministic. It is likely that the core executing the C SMM handler is not the same one that actually did the IO write to 0xB2 and generated the SMI. The GSMI parameter buffer is passed as a pointer to EBX in the tate save area, and the GSMI command is extracted from EAX before it is used as the return value. This interface is tested by enabling CONFIG_GOOGLE_GSMI in the kernel and generating events and verifying that they end up in the event log. 159 | 2012-06-23 16:22:45 | Kernl Event | Clean Shutdown 184 | 2012-06-23 17:14:05 | Kernl Event | Oops 185 | 2012-06-23 17:14:05 | Kernl Event | Panic Change-Id: Ic121ea69e9f50c88467c435e095c3e3629989806 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1317 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/usb_ehci.c')
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