diff options
author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/southbridge/intel/bd82x6x/usb_ehci.c | |
parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/usb_ehci.c')
-rw-r--r-- | src/southbridge/intel/bd82x6x/usb_ehci.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index e98b8bef7a..6cf4c1061b 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -35,7 +35,7 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); /* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if CONFIG(USE_NATIVE_RAMINIT) pci_write_config32(dev, 0x84, 0x930c8811); pci_write_config32(dev, 0x88, 0x24000d30); pci_write_config32(dev, 0xf4, 0x80408588); @@ -50,7 +50,7 @@ static void usb_ehci_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); /* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if CONFIG(USE_NATIVE_RAMINIT) struct resource *res; u8 access_cntl; |