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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-26 08:50:53 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-08-09 23:20:52 +0200
commitfd98c65b9d89e1ca665e25b6abf6d2019855e85a (patch)
tree17f16d8659ca8056aa06a2628bec4c7da1cea827 /src/southbridge/intel/bd82x6x/spi.c
parent0cc33da5530cf2ef776fc9fa2dbb80bb4dc4c830 (diff)
intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I58c4b021ac87a035ac2ec2b6b110b75e6d263ab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3810 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/spi.c')
-rw-r--r--src/southbridge/intel/bd82x6x/spi.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 320cf8cc6b..ec5d7de33e 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -36,17 +36,17 @@
#ifdef __SMM__
#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
- *(targ) = pcie_read_config8(dev, reg)
+ *(targ) = pci_read_config8(dev, reg)
#define pci_read_config_word(dev, reg, targ)\
- *(targ) = pcie_read_config16(dev, reg)
+ *(targ) = pci_read_config16(dev, reg)
#define pci_read_config_dword(dev, reg, targ)\
- *(targ) = pcie_read_config32(dev, reg)
+ *(targ) = pci_read_config32(dev, reg)
#define pci_write_config_byte(dev, reg, val)\
- pcie_write_config8(dev, reg, val)
+ pci_write_config8(dev, reg, val)
#define pci_write_config_word(dev, reg, val)\
- pcie_write_config16(dev, reg, val)
+ pci_write_config16(dev, reg, val)
#define pci_write_config_dword(dev, reg, val)\
- pcie_write_config32(dev, reg, val)
+ pci_write_config32(dev, reg, val)
#else /* !__SMM__ */
#include <device/device.h>
#include <device/pci.h>