diff options
| author | Marc Jones <marc.jones@se-eng.com> | 2012-11-13 15:07:45 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2013-03-09 00:09:37 +0100 |
| commit | e7ae96f48834d57fd1a6c8940fa3f64b97520ed9 (patch) | |
| tree | 34a5d2b6bb7bf08b82b5d1a8bf88c94294c704f7 /src/southbridge/intel/bd82x6x/smihandler.c | |
| parent | 4733c647bc64cef86f03efd64a145e4da6fef123 (diff) | |
Add Intel Panther Point USB3 initialization
Add PEI updates and ACPI updates for supporting EHCI to XHCI
USB port support.
Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2519
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/smihandler.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/smihandler.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 420c5db211..093da5c60a 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -326,6 +326,17 @@ static void southbridge_gate_memory_reset(void) outl(reg32, gpiobase + GP_LVL2); } +static void xhci_sleep(u8 slp_typ) +{ + u32 reg32; + + if (slp_typ == SLP_TYP_S5) { + reg32 = pcie_read_config32(PCH_XHCI_DEV, 0x74); + reg32 |= (1 << 8 | 0x03 ); + pcie_write_config32(PCH_XHCI_DEV, 0x74, reg32); + } +} + static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) { u8 reg8; @@ -353,6 +364,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = (reg32 >> 10) & 7; + if (smm_get_gnvs()->xhci) + xhci_sleep(slp_typ); + /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); if (mainboard_sleep) |