diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-28 19:50:44 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-02 07:43:31 +0000 |
| commit | 729c0695e5e93d7f7e48ddd72787769ff62cd8b9 (patch) | |
| tree | 2a38d3c9e946a5626669e787441bf4191c116068 /src/southbridge/intel/bd82x6x/smihandler.c | |
| parent | c5dd57ab655ba6b82c1adb9f58861155852e39fb (diff) | |
sb/intel/bd82x6x: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I1589fd8df4ec0fcdcde283513734dfd8458df2f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/smihandler.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/smihandler.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f778f7aec1..57b595999a 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -93,7 +93,7 @@ void southbridge_gate_memory_reset(void) static void xhci_sleep(u8 slp_typ) { - u32 reg32, xhci_bar; + u32 xhci_bar; u16 reg16; switch (slp_typ) { @@ -103,9 +103,8 @@ static void xhci_sleep(u8 slp_typ) reg16 &= ~0x03UL; pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); - reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); - reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL; @@ -119,9 +118,9 @@ static void xhci_sleep(u8 slp_typ) if ((xhci_bar + 0x4F0) & 1) pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); - reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_XHCI_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(PCH_XHCI_DEV, PCI_COMMAND, reg16); reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 |= 0x03; |