diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-10-03 19:11:26 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-11-14 05:44:18 +0100 |
| commit | 7978e3a3839b69c5b65de8dd8f35b4ffb8e27d93 (patch) | |
| tree | d718be8af8e7f90c56fbb6180525a6b8219ac657 /src/southbridge/intel/bd82x6x/smi.c | |
| parent | 7f3d442abb2a8ff6f6728527ab7665fd79fd60cd (diff) | |
SMM: Pass the ACPI GNVS pointer via state save map
Instead of hijacking some random memory addresses to
relay the GNVS pointer to SMM we can use EBX register
during the write to APM_CNT register when the SMI is
triggered.
Change-Id: I79a89512c40353d72ad058cbf2e6a23a696945da
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1766
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/smi.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/smi.c | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index bd88df2066..c89ae18636 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -398,11 +398,19 @@ void smm_lock(void) void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { - /* The GDT or coreboot table is going to live here. But a long time - * after we relocated the GNVS, so this is not troublesome. + /* + * Issue SMI to set the gnvs pointer in SMM. + * tcg and smi1 are unused. + * + * EAX = APM_CNT_GNVS_UPDATE + * EBX = gnvs pointer + * EDX = APM_CNT */ - *(u32 *)0x500 = (u32)gnvs; - *(u32 *)0x504 = (u32)tcg; - *(u32 *)0x508 = (u32)smi1; - outb(0xea, 0xb2); + asm volatile ( + "outb %%al, %%dx\n\t" + : /* ignore result */ + : "a" (APM_CNT_GNVS_UPDATE), + "b" ((u32)gnvs), + "d" (APM_CNT) + ); } |