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| author | Vadim Bendebury <vbendeb@chromium.org> | 2012-04-07 02:11:36 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-01 20:03:31 +0200 |
| commit | 459b7777fe871c5c9bd6636b1b13efc784129e31 (patch) | |
| tree | 17aee27897cd9ecee5ee16fae6f0031793d1bf9a /src/southbridge/intel/bd82x6x/smbus.c | |
| parent | 8049fc91ded9d780b9f6d5c40bc43ad3242b7a3b (diff) | |
add new LPC controller device ID value
This adds the PCI device id of the LPC controller identifying the
QPRJ/QS stepping of the Panther Point southbridge.
Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/968
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/smbus.c')
0 files changed, 0 insertions, 0 deletions