diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-07 22:09:01 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 18:48:32 +0000 |
| commit | c803f65206188ca74526054c54bce4f405a55850 (patch) | |
| tree | 9ce8dd5df1ac5e56912bb0f72c19274bfcfd0acb /src/southbridge/intel/bd82x6x/sata.c | |
| parent | 7333ea91eae33a874cf5187bc04906f6d2f1e3bf (diff) | |
sb/intel/bd82x6x: Use PCI bitwise ops
Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/sata.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/sata.c | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 1974e2b855..63801a213e 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -138,8 +138,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); /* Initialize AHCI memory-mapped space */ abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); @@ -172,9 +171,7 @@ static void sata_init(struct device *dev) /* IDE */ /* Without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); if (sata_mode == 1) { /* Native mode on both primary and secondary. */ @@ -182,7 +179,7 @@ static void sata_init(struct device *dev) printk(BIOS_DEBUG, "SATA: Controller in IDE compat mode.\n"); } else { /* Legacy mode on both primary and secondary. */ - pci_update_config8(dev, 0x09, ~0x05, 0x00); + pci_and_config8(dev, 0x09, ~0x05); printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n"); } @@ -191,14 +188,10 @@ static void sata_init(struct device *dev) pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* Port enable + OOB retry mode */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map | 0x8000; - pci_write_config16(dev, 0x92, reg16); + pci_update_config16(dev, 0x92, ~0x3f, config->sata_port_map | 0x8000); /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } /* Set Gen3 Transmitter settings if needed */ |