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| author | Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> | 2022-09-02 19:26:26 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-07 09:17:58 +0000 |
| commit | 60ef19bcf38bb5311d517c809c424b226d7ad1c4 (patch) | |
| tree | f0308a0d58ffbc3c9b2f592ea57e9ec3a3d5e3f1 /src/southbridge/intel/bd82x6x/pcie.c | |
| parent | fc71ea82f9174169f274e1006c77c53e669c42e0 (diff) | |
mb/google/corsola: Fix ANX7625 power-on T4 sequence
The T4 of ANX7625 power on sequence should be larger than 0ms, but it's
-59ms now. So add 70ms delay between DSI_TE and LCM_RST.
BUG=b:242352915
TEST=The sequence T4 is larger than 0ms when power on.
Change-Id: I6b888707ec3c0612e396564e77c4cdbe92614dc5
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pcie.c')
0 files changed, 0 insertions, 0 deletions