diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-06-07 22:09:01 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 18:48:32 +0000 |
commit | c803f65206188ca74526054c54bce4f405a55850 (patch) | |
tree | 9ce8dd5df1ac5e56912bb0f72c19274bfcfd0acb /src/southbridge/intel/bd82x6x/pcie.c | |
parent | 7333ea91eae33a874cf5187bc04906f6d2f1e3bf (diff) |
sb/intel/bd82x6x: Use PCI bitwise ops
Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pcie.c')
-rw-r--r-- | src/southbridge/intel/bd82x6x/pcie.c | 52 |
1 files changed, 14 insertions, 38 deletions
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index ff881ac20e..c381d33b57 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -109,9 +109,7 @@ static void pch_pcie_pm_early(struct device *dev) pci_write_config8(dev, 0xe1, reg8); /* Set 0xE8[0] = 1 */ - reg32 = pci_read_config32(dev, 0xe8); - reg32 |= 1; - pci_write_config32(dev, 0xe8, reg32); + pci_or_config32(dev, 0xe8, 1); /* Adjust Common Clock exit latency */ reg32 = pci_read_config32(dev, 0xd8); @@ -144,38 +142,24 @@ static void pch_pcie_pm_late(struct device *dev) { struct southbridge_intel_bd82x6x_config *config = dev->chip_info; enum aspm_type apmc = 0; - u32 reg32; /* Set 0x314 = 0x743a361b */ pci_write_config32(dev, 0x314, 0x743a361b); /* Set 0x318[31:16] = 0x1414 */ - reg32 = pci_read_config32(dev, 0x318); - reg32 &= 0x0000ffff; - reg32 |= 0x14140000; - pci_write_config32(dev, 0x318, reg32); + pci_update_config32(dev, 0x318, 0x0000ffff, 0x14140000); /* Set 0x324[5] = 1 */ - reg32 = pci_read_config32(dev, 0x324); - reg32 |= (1 << 5); - pci_write_config32(dev, 0x324, reg32); + pci_or_config32(dev, 0x324, 1 << 5); /* Set 0x330[7:0] = 0x40 */ - reg32 = pci_read_config32(dev, 0x330); - reg32 &= ~(0xff); - reg32 |= 0x40; - pci_write_config32(dev, 0x330, reg32); + pci_update_config32(dev, 0x330, ~0xff, 0x40); /* Set 0x33C[24:0] = 0x854c74 */ - reg32 = pci_read_config32(dev, 0x33c); - reg32 &= 0xff000000; - reg32 |= 0x00854c74; - pci_write_config32(dev, 0x33c, reg32); + pci_update_config32(dev, 0x33c, 0xff000000, 0x00854c74); /* No IO-APIC, Disable EOI forwarding */ - reg32 = pci_read_config32(dev, 0xd4); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xd4, reg32); + pci_or_config32(dev, 0xd4, 1 << 1); /* Check for a rootport ASPM override */ switch (PCI_FUNC(dev->path.pci.devfn)) { @@ -207,19 +191,15 @@ static void pch_pcie_pm_late(struct device *dev) /* Setup the override or get the real ASPM setting */ if (apmc) { - reg32 = pci_read_config32(dev, 0xd4); - reg32 |= (apmc << 2) | (1 << 4); - pci_write_config32(dev, 0xd4, reg32); + pci_or_config32(dev, 0xd4, (apmc << 2) | (1 << 4)); + } else { apmc = pci_read_config32(dev, 0x50) & 3; } /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ - if (apmc == PCIE_ASPM_BOTH) { - reg32 = pci_read_config32(dev, 0xe8); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xe8, reg32); - } + if (apmc == PCIE_ASPM_BOTH) + pci_or_config32(dev, 0xe8, 1 << 1); } static void pci_init(struct device *dev) @@ -236,10 +216,8 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 |= PCI_BRIDGE_CTL_NO_ISA; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + pci_update_config16(dev, PCI_BRIDGE_CONTROL, + ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA); #ifdef EVEN_MORE_DEBUG u32 reg32; @@ -253,7 +231,7 @@ static void pci_init(struct device *dev) printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); #endif - /* Clear errors in status registers */ + /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, 0x06); //reg16 |= 0xf900; pci_write_config16(dev, 0x06, reg16); @@ -264,9 +242,7 @@ static void pci_init(struct device *dev) /* Enable expresscard hotplug events. */ if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { - pci_write_config32(dev, 0xd8, - pci_read_config32(dev, 0xd8) - | (1 << 30)); + pci_or_config32(dev, 0xd8, 1 << 30); pci_write_config16(dev, 0x42, 0x142); } } |