diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2023-09-26 17:27:05 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-09 13:59:16 +0000 |
| commit | f1b5b0dfa6b025ab74def496a6352414df7dc6b5 (patch) | |
| tree | c01c732d6b14e359c328030a88cb2cc976044fd8 /src/southbridge/intel/bd82x6x/pcie.c | |
| parent | 873178bfd64fe98558cc50e35977c7cc380374d5 (diff) | |
soc/mediatek: PCI: Fix translation window
Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN
enabled. The root cause is using __fls() will get a smaller value when
the size is not a power of 2, for example, __fls(0x3000000) = 25. Hence
the PCIe translation window size is set to 0x2000000. Accessing
addresses higher than 0x2300000 will fail.
Fix translation window by splitting the MMIO space to multiple tables if
its size is not a power of 2.
Resolves: https://ticket.coreboot.org/issues/508.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, it can boot with and without the
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN option.
BUS=b:298255933
BRANCH=cherry
Change-Id: I42b0f0bf9222d284dee0c29f1a6ed6366d6e6689
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78044
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pcie.c')
0 files changed, 0 insertions, 0 deletions