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authorSubrata Banik <subratabanik@google.com>2024-07-09 23:18:18 +0530
committerSubrata Banik <subratabanik@google.com>2024-07-11 15:24:07 +0000
commitdf052ff30ef328b82d25319f1bacb107d3b54225 (patch)
tree1c80d81bff031a375b68238bbfb1761383801288 /src/southbridge/intel/bd82x6x/pci.c
parent62347c4669937ea47200fd677ad0368f6e289495 (diff)
soc/intel: Extend CSE RW Update and ME read access for payload sync
Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and `ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`. This allows these features to be enabled even when CSE sync is performed in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU` config is enabled). BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pci.c')
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