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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-24 20:27:28 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-26 16:54:04 +0200 |
| commit | 0739b9fe85142051bb121c74ce9436ed030e7347 (patch) | |
| tree | c74de1f6813a4ef4802b9f9c79c789f86736f4b1 /src/southbridge/intel/bd82x6x/pci.c | |
| parent | 3242bcfa0feb50160dc0e6059216a5c1a0626031 (diff) | |
nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines
The wrong DIMM number was used in the initial non-target MRS
setup routines. This had no functional impact other than to
print the wrong DIMM number in the DDR3 verbose debug output.
Change-Id: I480118ed00e1786a06e641a56f0fb19cd87f92eb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14501
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pci.c')
0 files changed, 0 insertions, 0 deletions