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| author | Tim Crawford <tcrawford@system76.com> | 2023-01-04 12:10:23 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-04 01:58:56 +0000 |
| commit | d5d56b3d42efeeebde9a8867d95e21d7b698aa18 (patch) | |
| tree | d9f6d465cf9afae344b4834ae930945bf02c49cc /src/southbridge/intel/bd82x6x/pch.h | |
| parent | e0c96daccedc12a31c52a5da3cfacdb4a61c2e9a (diff) | |
mb/system76/tgl-u: Leave TBT LSX0 as FSP configured
Do not reconfigured LSX0 so that the FSP values are used.
Change-Id: I7ef4af2cde4f3260f2bc2efdbf85569b0eb147fb
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
0 files changed, 0 insertions, 0 deletions