diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-10-11 13:04:14 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-11-12 17:09:59 +0100 |
| commit | d4bc0679540842d78712b41707c2da9f3d7ae204 (patch) | |
| tree | 30ef0888bd8fec4b86759769bf7bad5477376baf /src/southbridge/intel/bd82x6x/pch.h | |
| parent | 215f27856399b1e4cfe30268fad61bf821af3c19 (diff) | |
SPI: Add early romstage SPI driver using hardware sequencing
This is a basic romstage driver that can be used for the
MRC cache code on systems where we do not have the MRC cache
stored in a flash region that is memory mapped.
It uses the hardware sequencing interface to avoid having
to know anything about the flash chip itself.
BUG=chrome-os-partner:15031
BRANCH=stout
TEST=manual: this was tested with debug code added to romstage
that attempted to read the MRC cache at offset 0x3e0000.
SPI READ offset=003e0000 size=64 buffer=ff7fba00
SPI ADDR 0x003e0000
SPI HSFC 0x3f00
SPI READ: 0=4443524d
SPI READ: 1=00000bb0
SPI READ: 2=00008e24
SPI READ: 3=00000000
SPI READ: 4=001c8bbb
SPI READ: 5=0c206466
SPI READ: 6=0a043220
SPI READ: 7=000058b4
SPI READ: 8=00000000
SPI READ: 9=00000000
SPI READ: 10=00100000
SPI READ: 11=00100005
SPI READ: 12=20202025
SPI READ: 13=000e0001
SPI READ: 14=00000000
SPI READ: 15=00000000
Change-Id: I5f78f53111f912ff5dda52bbf90fdc1824b82681
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1777
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 40c97fd2f3..121167178f 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -71,6 +71,7 @@ void pch_log_state(void); void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); +int early_spi_read(u32 offset, u32 size, u8 *buffer); #endif #endif @@ -539,5 +540,19 @@ int smbus_read_byte(unsigned device, unsigned address); #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ +#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ +#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ +#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ +#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ +#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ +#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) +#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ +#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ +#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ +#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ +#define SPIBAR_FADDR 0x3808 /* SPI flash address */ +#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ + #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ |