diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-07-16 16:16:31 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-26 20:29:16 +0200 |
| commit | cfb64bda83f5f47762845b8b6666783bae82ec34 (patch) | |
| tree | dfd8883996fa9933ba50226eb57df9bd11cc4ab2 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | 0920915bca2391ed318eeb12ddad8b7cb4a52905 (diff) | |
SATA: Add option to configure gen3 transmitter
Unfortunately the drive strength values are very much board
specific and different between mobile and desktop so we don't
try to do any fancy detection here but let it be specified
directly in the devicetree.
Change-Id: I66674bff0de04ecd088fb09afad1cf801a374df2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1347
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 0a16308f9b..beed63a20e 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -198,6 +198,10 @@ int smbus_read_byte(unsigned device, unsigned address); #define SATA_SP 0xd0 /* Scratchpad */ +/* SATA IOBP Registers */ +#define SATA_IOBP_SP0G3IR 0xea000151 +#define SATA_IOBP_SP1G3IR 0xea000051 + /* PCI Configuration Space (D31:F3): SMBus */ #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) #define SMB_BASE 0x20 |