diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-06 00:48:39 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-13 12:13:45 +0000 |
| commit | 2fa7f07fada00eb031360797a689e38551802114 (patch) | |
| tree | 20713f3213037dc58e9158e8eacb2c9f0b28b466 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | 50a80b3d08306958bf0151223ac70bee471fed56 (diff) | |
sb/intel/bd82x6x: Correct xHCI sleep workaround
The S3/S4 workaround is specific to Panther Point stepping A0, and it is
wrongly implemented. Rewrite the whole function as per reference code.
Since this runs in SMM, be overly cautious and double-check everything.
Do not rely on GNVS to determine if xHCI is enabled. Instead, check
whether the corresponding bit in the Function Disable register is set.
Only Panther Point has xHCI, so exit early if this is not the case.
Change-Id: Iabce6c52fac781dc694f5b589fab2e9fe438f3f5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 151627d5dd..1840a2b0d2 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -84,7 +84,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) -#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_PCIE_DEV_SLOT 28 #define PCH_IOAPIC_PCI_BUS 250 @@ -92,6 +91,14 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define PCH_HPET_PCI_BUS 250 #define PCH_HPET_PCI_SLOT 15 +/* PCI Configuration Space (D20:F0): xHCI */ +#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) + +#define XHCI_PWR_CNTL_STS 0x74 + +/* xHCI memory base registers */ +#define XHCI_PORTSC_x_USB3(port) (0x4c0 + (port) * 0x10) + /* PCI Configuration Space (D31:F0): LPC */ #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIRQ_CNTL 0x64 |