diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-24 14:47:47 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-04-16 08:58:50 +0000 |
| commit | e2f0a5f76c8a525396f627b8ba97e8913ab14fc6 (patch) | |
| tree | 201919537965cd897ad3e50afe07b1ea4153a050 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | ad0b48222ffd894f1b8f78e7de8a6ee139fc17c9 (diff) | |
sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3.
Tested on Lenovo T520 (Intel Sandy Bridge) with Change
I8afc9f966033f45823f5dfde279e0f66de165e93 applied as well.
Still boots to OS, no errors visible in dmesg and S3 resume is working.
Change-Id: I283a841575430f2f179997db8d2f08fa3978a0bb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 67b0d11415..741996531f 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -76,7 +76,6 @@ void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); -int southbridge_detect_s3_resume(void); struct southbridge_usb_port { |