diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-10-08 14:30:06 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-12 04:22:57 +0100 |
| commit | 924342bb2b9e429d66a693503c9f944655da4bb8 (patch) | |
| tree | 835cf560582f2bf316acd490072cb04f1c68dfb6 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | fb8632ab58de871ef3a25b5e57c7a2e95f04a0d8 (diff) | |
SPI: Add Fast Read to the OPMENU for locked down SPI
The chips we are using do not use BE52 (block erase 0x52)
so we can use that opcode menu location to enable fast read.
Change-Id: I18f3e0e5e462b052358654faa0c82103b23a9f61
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 84815545c3..40c97fd2f3 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -524,8 +524,8 @@ int smbus_read_byte(unsigned device, unsigned address); #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ #define SPI_OPTYPE_6 0x03 /* Write, address required */ -#define SPI_OPMENU_7 0x52 /* BE52: Block Erase 0x52 */ -#define SPI_OPTYPE_7 0x03 /* Write, address required */ +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) |