sb/intel/bd82x6x: Add and use more RCBA defines

Taken from
"Intel 6 Series Chipset and Intel C200 Series Chipset"
Document Number: 324645-006 and
"Intel 5 Series Chipset and Intel 3400 Series Chipset"
Document Number: 322169-004 and
"Intel 6 Series Chipset"
Document Number: 324645-001.

UPDCR was found in GNU/Linux's drivers/pci/quirks.c.
DMC2 was guessed as it's close to DMC and defined for 5 series chipset.

Test:
Run BUILD_TIMELESS=1 and compared the coreboot.roms, no differences.

Change-Id: I4fed7c38078cabd4308424c7547416e87c9e6fa7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 74 insertions, 13 deletions

diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 4369b5c162..bc6c8b333f 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -256,19 +256,8 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 
 #define PMBASE		0x40
 
-#define VCH		0x0000	/* 32bit */
-#define VCAP1		0x0004	/* 32bit */
-#define VCAP2		0x0008	/* 32bit */
-#define PVC		0x000c	/* 16bit */
-#define PVS		0x000e	/* 16bit */
-
-#define V0CAP		0x0010	/* 32bit */
-#define V0CTL		0x0014	/* 32bit */
-#define V0STS		0x001a	/* 16bit */
-
-#define V1CAP		0x001c	/* 32bit */
-#define V1CTL		0x0020	/* 32bit */
-#define V1STS		0x0026	/* 16bit */
+#define CIR0		0x0050	/* 32bit */
+#define  TCLOCKDN	(1u << 31)
 
 #define RCTCL		0x0100	/* 32bit */
 #define ESD		0x0104	/* 32bit */
@@ -293,6 +282,10 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 #define RPC		0x0400	/* 32bit */
 #define RPFN		0x0404	/* 32bit */
 
+#define CIR2		0x900	/* 16bit */
+#define CIR3		0x1100	/* 16bit */
+#define UPDCR		0x1114	/* 32bit */
+
 /* Root Port configuratinon space hide */
 #define RPFN_HIDE(port)         (1 << (((port) * 4) + 3))
 /* Get the function number assigned to a Root Port */
@@ -335,6 +328,27 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 #define PIRQG		6
 #define PIRQH		7
 
+/* DMI control */
+#define V0CTL		0x2014	/* 32bit */
+#define V0STS		0x201a	/* 16bit */
+#define V1CTL		0x2020	/* 32bit */
+#define V1STS		0x2026	/* 16bit */
+#define CIR31		0x2030	/* 32bit */
+#define CIR32		0x2040	/* 32bit */
+#define CIR1		0x2088	/* 32bit */
+#define REC		0x20ac	/* 32bit */
+#define LCAP		0x21a4	/* 32bit */
+#define LCTL		0x21a8	/* 16bit */
+#define LSTS		0x21aa	/* 16bit */
+#define DLCTL2		0x21b0	/* 16bit */
+#define DMIC		0x2234	/* 32bit */
+#define CIR30		0x2238	/* 32bit */
+#define CIR5		0x228c	/* 32bit */
+#define DMC		0x2304	/* 32bit */
+#define CIR6		0x2314	/* 32bit */
+#define CIR9		0x2320	/* 32bit */
+#define DMC2		0x2324	/* 32bit - name guessed */
+
 /* IO Buffer Programming */
 #define IOBPIRI		0x2330
 #define IOBPD		0x2334
@@ -391,6 +405,26 @@ early_usb_init (const struct southbridge_usb_port *portmap);
   RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
                ((b) << DIR_IBR) | ((a) << DIR_IAR))
 
+#define PRSTS		0x3310	/* 32bit */
+#define CIR7		0x3314	/* 32bit */
+#define PM_CFG		0x3318	/* 32bit */
+#define CIR8		0x3324	/* 32bit */
+#define CIR10		0x3340	/* 32bit */
+#define CIR11		0x3344	/* 32bit */
+#define CIR12		0x3360	/* 32bit */
+#define CIR14		0x3368	/* 32bit */
+#define CIR15		0x3378	/* 32bit */
+#define CIR13		0x337c	/* 32bit */
+#define CIR16		0x3388	/* 32bit */
+#define CIR18		0x3390	/* 32bit */
+#define CIR17		0x33a0	/* 32bit */
+#define CIR23		0x33b0	/* 32bit */
+#define CIR19		0x33c0	/* 32bit */
+#define PMSYNC_CFG	0x33c8	/* 32bit */
+#define CIR20		0x33cc	/* 32bit */
+#define CIR21		0x33d0	/* 32bit */
+#define CIR22		0x33d4	/* 32bit */
+
 #define RC		0x3400	/* 32bit */
 #define HPTC		0x3404	/* 32bit */
 #define GCS		0x3410	/* 32bit */
@@ -422,11 +456,38 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 #define PCH_DISABLE_MEI1	(1 << 1)
 #define PCH_ENABLE_DBDF		(1 << 0)
 
+/* USB Initialization Registers[13:0] */
+#define USBIR0		0x3500	/* 32bit */
+#define USBIR1		0x3504	/* 32bit */
+#define USBIR2		0x3508	/* 32bit */
+#define USBIR3		0x350c	/* 32bit */
+#define USBIR4		0x3510	/* 32bit */
+#define USBIR5		0x3514	/* 32bit */
+#define USBIR6		0x3518	/* 32bit */
+#define USBIR7		0x351c	/* 32bit */
+#define USBIR8		0x3520	/* 32bit */
+#define USBIR9		0x3524	/* 32bit */
+#define USBIR10		0x3528	/* 32bit */
+#define USBIR11		0x352c	/* 32bit */
+#define USBIR12		0x3530	/* 32bit */
+#define USBIR13		0x3534	/* 32bit */
+
+/* Miscellaneous Control Register */
+#define MISCCTL		0x3590	/* 32bit */
 /* USB Port Disable Override */
 #define USBPDO		0x359c	/* 32bit */
 /* USB Overcurrent MAP Register */
 #define USBOCM1		0x35a0	/* 32bit */
 #define USBOCM2		0x35a4	/* 32bit */
+/* Rate Matching Hub Wake Control Register */
+#define RMHWKCTL	0x35b0	/* 32bit */
+
+#define CIR24		0x3a28	/* 32bit */
+#define CIR25		0x3a2c	/* 32bit */
+#define CIR26		0x3a6c	/* 32bit */
+#define CIR27		0x3a80	/* 32bit */
+#define CIR28		0x3a84	/* 32bit */
+#define CIR29		0x3a88	/* 32bit */
 
 /* XHCI USB 3.0 */
 #define XOCM		0xc0	/* 32bit */