aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/intel/bd82x6x/me.h
diff options
context:
space:
mode:
authorStefan Reinauer <reinauer@chromium.org>2012-06-11 15:15:46 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-24 23:17:17 +0200
commit998f3a27be2a16ae0bc1f193a805b680208d63ab (patch)
treeeab8d4c149630e72d4ff47e698883ddcbc92f1fc /src/southbridge/intel/bd82x6x/me.h
parent49058c0adf348342ea23711f018997816da4056b (diff)
Cougar/Panther Point: Compile in ME7 and ME8 code at the same time
In the short term there might be devices with Sandy Bridge CPUs on mainboards with Panther Point PCHes. While this configuration option is perfectly valid, coreboot currently ties Sandy Bridge to Cougar Point and Ivy Bridge to Panther Point. One occurence is in the ME handling code. To make coreboot most flexible, compile both ME handlers into coreboot and decide at runtime which one to use. Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1280 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/me.h')
-rw-r--r--src/southbridge/intel/bd82x6x/me.h5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index 53964a2faa..aaeb24d65d 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -248,14 +248,11 @@ void intel_early_me_status(void);
int intel_early_me_init(void);
int intel_early_me_uma_size(void);
int intel_early_me_init_done(u8 status);
-#else
-/* ME Kernel Host Interface Messages */
-int mkhi_end_of_post(void);
-int mkhi_global_reset(void);
#endif
#ifdef __SMM__
void intel_me_finalize_smm(void);
+void intel_me8_finalize_smm(void);
#endif
typedef struct {
u32 major_version : 16;