diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-06-11 15:15:46 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 23:17:17 +0200 |
| commit | 998f3a27be2a16ae0bc1f193a805b680208d63ab (patch) | |
| tree | eab8d4c149630e72d4ff47e698883ddcbc92f1fc /src/southbridge/intel/bd82x6x/me.c | |
| parent | 49058c0adf348342ea23711f018997816da4056b (diff) | |
Cougar/Panther Point: Compile in ME7 and ME8 code at the same time
In the short term there might be devices with Sandy Bridge CPUs
on mainboards with Panther Point PCHes. While this configuration
option is perfectly valid, coreboot currently ties Sandy Bridge to
Cougar Point and Ivy Bridge to Panther Point. One occurence is in
the ME handling code.
To make coreboot most flexible, compile both ME handlers into
coreboot and decide at runtime which one to use.
Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1280
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/me.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me.c | 23 |
1 files changed, 20 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 1b7b2623c2..0c40ab4276 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -353,8 +353,9 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, return 0; } +#ifdef __SMM__ /* Send END OF POST message to the ME */ -int mkhi_end_of_post(void) +static int mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -376,6 +377,7 @@ int mkhi_end_of_post(void) printk(BIOS_INFO, "ME: END OF POST message successful\n"); return 0; } +#endif #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) /* Get ME firmware version */ @@ -460,6 +462,7 @@ static int mkhi_get_fwcaps(void) } #endif +#if CONFIG_CHROMEOS && 0 /* DISABLED */ /* Tell ME to issue a global reset */ int mkhi_global_reset(void) { @@ -490,10 +493,10 @@ int mkhi_global_reset(void) printk(BIOS_ERR, "ME: Global Reset failed\n"); return -1; } +#endif #ifdef __SMM__ - -void intel_me_finalize_smm(void) +static void intel_me7_finalize_smm(void) { struct me_hfs hfs; u32 reg32; @@ -528,6 +531,20 @@ void intel_me_finalize_smm(void) RCBA32_OR(FD2, PCH_DISABLE_MEI1); } +void intel_me_finalize_smm(void) +{ + u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + switch (did) { + case 0x80861c3a: + intel_me7_finalize_smm(); + break; + case 0x80861e3a: + intel_me8_finalize_smm(); + break; + default: + printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); + } +} #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ |