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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-29 23:14:53 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-02-06 07:16:16 +0000
commit8fee9951d30d03b4bca16c198b887c5415418c12 (patch)
tree929be61cb85aee7c83bcc4e91f82ef379e960b60 /src/southbridge/intel/bd82x6x/include/soc/nvs.h
parent68d68f1d7c7693f7e49634b6c2106d3c2630d4b0 (diff)
sb,soc/intel: Add wake source fields in GNVS
For the moment, these are most not used but become a necessity for a unified <soc/nvs.h> approach. They would be required for the implementation of _SWS method for OSPM to determine the reason for system waking up. The related hardware registers are present with these platforms. It's expected that ACPI power-management related GNVS entries are grouped together to form a single struct in later works. Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/include/soc/nvs.h')
-rw-r--r--src/southbridge/intel/bd82x6x/include/soc/nvs.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
index 969d59209b..1c33b0cd73 100644
--- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h
+++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
@@ -97,7 +97,11 @@ struct __packed global_nvs {
u8 rsvd11[6];
/* XHCI */
u8 xhci;
- u8 rsvd12[65];
+
+ /* Required for future unified acpi_save_wake_source. */
+ u32 pm1i;
+ u32 gpei;
+ u8 rsvd12[57];
u8 tpiq; /* 0xf5 - trackpad IRQ value */
u32 cbmc;