diff options
| author | Nico Huber <nico.h@gmx.de> | 2017-09-01 23:28:14 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-09-22 19:17:49 +0000 |
| commit | 2ac149d294af795710eb4bb20f093e9920604abd (patch) | |
| tree | 23f9b07ad2e5e8b2af14aaef8570e999e89a599e /src/southbridge/intel/bd82x6x/finalize.c | |
| parent | 7eb0157fca33865783c1cc3c8e5cb2e327e551d7 (diff) | |
sb/intel/bd82x6x: Revise flash ROM lockdown options
The original options were named and described under the false assumption
that the chipset lockdown would only be executed during S3 resume. Fix
that.
Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/finalize.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/finalize.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index a9cfa38c63..fe28af0385 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -25,12 +25,13 @@ void intel_pch_finalize_smm(void) u16 tco1_cnt; u16 pmbase; - if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) { + if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) || + IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) { /* Copy flash regions from FREG0-4 to PR0-4 and enable write protection bit31 */ int i; u32 lockmask = (1 << 31); - if (CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) + if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) lockmask |= (1 << 15); for (i = 0; i < 20; i += 4) RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; |