diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-28 19:50:44 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-02 07:43:31 +0000 |
| commit | 729c0695e5e93d7f7e48ddd72787769ff62cd8b9 (patch) | |
| tree | 2a38d3c9e946a5626669e787441bf4191c116068 /src/southbridge/intel/bd82x6x/early_usb_mrc.c | |
| parent | c5dd57ab655ba6b82c1adb9f58861155852e39fb (diff) | |
sb/intel/bd82x6x: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I1589fd8df4ec0fcdcde283513734dfd8458df2f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/early_usb_mrc.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_usb_mrc.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index 0896a4d966..f60cc0b706 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -18,19 +18,14 @@ void enable_usb_bar(void) { pci_devfn_t usb0 = PCH_EHCI1_DEV; pci_devfn_t usb1 = PCH_EHCI2_DEV; - u32 cmd; /* USB Controller 1 */ pci_write_config32(usb0, PCI_BASE_ADDRESS_0, PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb0, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb0, PCI_COMMAND, cmd); + pci_or_config16(usb0, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* USB Controller 2 */ pci_write_config32(usb1, PCI_BASE_ADDRESS_0, PCH_EHCI2_TEMP_BAR0); - cmd = pci_read_config32(usb1, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb1, PCI_COMMAND, cmd); + pci_or_config16(usb1, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } |