diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-07 22:09:01 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 18:48:32 +0000 |
| commit | c803f65206188ca74526054c54bce4f405a55850 (patch) | |
| tree | 9ce8dd5df1ac5e56912bb0f72c19274bfcfd0acb /src/southbridge/intel/bd82x6x/early_thermal.c | |
| parent | 7333ea91eae33a874cf5187bc04906f6d2f1e3bf (diff) | |
sb/intel/bd82x6x: Use PCI bitwise ops
Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/early_thermal.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_thermal.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 0abd85cbbb..b3510ac521 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -38,7 +38,7 @@ void early_thermal_init(void) pci_write_config32(dev, 0x44, 0x0); /* Activate temporary BAR. */ - pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5); + pci_or_config32(dev, 0x40, 5); write16p(TBARB_TEMP + 0x04, 0x3a2b); @@ -61,7 +61,8 @@ void early_thermal_init(void) write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0); /* Disable temporary BAR */ - pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); + pci_and_config32(dev, 0x40, ~1); + pci_write_config32(dev, 0x40, 0); write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); |