diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2017-09-15 15:19:32 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-20 23:54:26 +0000 |
| commit | 976200388b6924c7b30c6062b64a8db7e215f37f (patch) | |
| tree | 659eca8c9acac2ffb13492086acca2b60ec099a7 /src/southbridge/intel/bd82x6x/early_pch_common.c | |
| parent | cfe7ad1e8f7ed6f3d72db2041bf2051ac88e2a5f (diff) | |
southbridge/intel/bd82x6x: refactor rtc failure checking
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to early_pch_common.c and
add a helper function to determine if failure occurred.
BUG=b:63054105
Change-Id: I710d99551cfb6455244f66b47fcbecc790ae770f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/early_pch_common.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch_common.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index d2789005f0..0ea3dff001 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -17,10 +17,13 @@ #include <arch/io.h> #include <timestamp.h> #include <cpu/x86/tsc.h> +#include <device/pci_def.h> #include "pch.h" #include <arch/acpi.h> #include <console/console.h> +#include <rules.h> +#if ENV_ROMSTAGE uint64_t get_initial_timestamp(void) { tsc_t base_time = { @@ -56,3 +59,14 @@ int southbridge_detect_s3_resume(void) return 0; } +#endif + +int rtc_failure(void) +{ +#if defined(__SIMPLE_DEVICE__) + device_t dev = PCI_DEV(0, 0x1f, 0); +#else + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); +#endif + return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); +} |