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authorNathaniel Roach <nroach44@gmail.com>2017-09-09 19:58:08 +0800
committerAaron Durbin <adurbin@chromium.org>2017-09-13 16:19:06 +0000
commit52f0871b23233ec7314cf778e5534d99dd85ff3d (patch)
tree6baf5418796144f56fd72a36a131dc92d709d755 /src/southbridge/intel/bd82x6x/early_me.c
parent3670cc1bad12522e3f9eb86d923c52d4016f90e9 (diff)
sb/intel/bd82x6x: Add time-stamp around ME DRAM update
Add a timestamp before and after waiting for the ME to acknowledge the DRAM being ready. This allows easier debugging during use of me_cleaner and/or alternate ME images. Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/21465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/early_me.c')
-rw-r--r--src/southbridge/intel/bd82x6x/early_me.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index 607cd14911..b2e920056d 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -20,6 +20,7 @@
#include <device/pci_ids.h>
#include <halt.h>
#include <string.h>
+#include <timestamp.h>
#include "me.h"
#include "pch.h"
@@ -190,6 +191,7 @@ int intel_early_me_init_done(u8 status)
meDID = did.uma_base | (1 << 28);// | (1 << 23);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);
+ timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);
udelay(1100);
/* Must wait for ME acknowledgement */
@@ -200,6 +202,7 @@ int intel_early_me_init_done(u8 status)
hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
millisec++;
}
+ timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);