diff options
| author | Marc Jones <marc.jones@se-eng.com> | 2012-10-31 16:24:37 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-12 04:23:56 +0100 |
| commit | 4adc8cdd185f46cd62f3bd17188761d3b0b1d87d (patch) | |
| tree | 6bef9a659fea70f23a42d0c18d81ec3eef685150 /src/southbridge/intel/bd82x6x/chip.h | |
| parent | 2a700ec16322561ad487e6ef1ae8878f9a7e4357 (diff) | |
Add bd82x6x mainboards ASPM overrides.
The Intel PCH can override the ASPM settings via the MPC2 register.
Add a chip override for F0-F7. Mainboards may implement this as
needed.
This also fixes the final PM setup being done too early. It was
being done prior to the PCIe ASPM setup, which happens in the
bridge scan.
Change-Id: Idf2d2374899873fc6b1a2b00abdb683ea9f5bd6b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1796
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/chip.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/chip.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 05eeab225d..092a8f11c7 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -77,6 +77,16 @@ struct southbridge_intel_bd82x6x_config { /* Enable linear PCIe Root Port function numbers starting at zero */ uint8_t pcie_port_coalesce; + + /* Override PCIe ASPM */ + uint8_t pcie_aspm_f0; + uint8_t pcie_aspm_f1; + uint8_t pcie_aspm_f2; + uint8_t pcie_aspm_f3; + uint8_t pcie_aspm_f4; + uint8_t pcie_aspm_f5; + uint8_t pcie_aspm_f6; + uint8_t pcie_aspm_f7; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ |