diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-07-14 11:54:58 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-07-18 05:42:55 +0000 |
| commit | 4f8b108288bf080762d28e5260ecf1d0a6e89697 (patch) | |
| tree | ba845049ec518bf2bea78e983360e525316a3dba /src/southbridge/intel/bd82x6x/azalia.c | |
| parent | 44443696afed62f074dab1468c270ab207f5bb69 (diff) | |
sb/intel/bd82x6x: Add and use more RCBA defines
Taken from
"Intel 6 Series Chipset and Intel C200 Series Chipset"
Document Number: 324645-006 and
"Intel 5 Series Chipset and Intel 3400 Series Chipset"
Document Number: 322169-004 and
"Intel 6 Series Chipset"
Document Number: 324645-001.
UPDCR was found in GNU/Linux's drivers/pci/quirks.c.
DMC2 was guessed as it's close to DMC and defined for 5 series chipset.
Test:
Run BUILD_TIMELESS=1 and compared the coreboot.roms, no differences.
Change-Id: I4fed7c38078cabd4308424c7547416e87c9e6fa7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/azalia.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/azalia.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 8d424b8ba6..e3379d6af0 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -242,11 +242,11 @@ static void azalia_init(struct device *dev) base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); - if (RCBA32(0x2030) & (1 << 31)) { + if (RCBA32(CIR31) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 24); // 2 << 24 for server - reg32 |= RCBA32(0x2030) & 0xfe; + reg32 |= RCBA32(CIR31) & 0xfe; pci_write_config32(dev, 0x120, reg32); reg16 = pci_read_config16(dev, 0x78); |