diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-29 23:14:53 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-06 07:16:16 +0000 |
| commit | 8fee9951d30d03b4bca16c198b887c5415418c12 (patch) | |
| tree | 929be61cb85aee7c83bcc4e91f82ef379e960b60 /src/southbridge/intel/bd82x6x/acpi | |
| parent | 68d68f1d7c7693f7e49634b6c2106d3c2630d4b0 (diff) | |
sb,soc/intel: Add wake source fields in GNVS
For the moment, these are most not used but become a necessity
for a unified <soc/nvs.h> approach.
They would be required for the implementation of _SWS method
for OSPM to determine the reason for system waking up. The related
hardware registers are present with these platforms.
It's expected that ACPI power-management related GNVS entries are
grouped together to form a single struct in later works.
Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/acpi')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index e873f55375..25dcfe0ffe 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -100,6 +100,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xb2), XHCI, 8, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value CBMC, 32, |