diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-09-19 10:32:25 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-09 19:04:06 +0100 |
| commit | 0acdcf614c9966112add57226e7473bccd86dd64 (patch) | |
| tree | 1f58b5ccdba6e8ebc2ddf0a3c99ab07648fe98a4 /src/southbridge/intel/bd82x6x/acpi | |
| parent | 4c8027abdd3492bc0507906ea3109c0420159ae0 (diff) | |
Add IGD Opregion variables to NVS
In order to support Intel's IGD Opregion standard, we need
an additional set of flags shared between firmware, ACPI, SMM, and the
graphics driver.
Change-Id: I1a9b8dff5e5ee8d501b6672bc3bcca39ea65572e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1750
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/acpi')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 7aeb32bc9b..2fe092d952 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -150,7 +151,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) I509, 8, // 0xc1 - IGD 0509 modified settings I609, 8, // 0xc2 - IGD 0609 modified settings I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode + IDMM, 8, // 0xc4 - IGD Power conservation feature IDMS, 8, // 0xc5 - IGD DVMT memory size IF1E, 8, // 0xc6 - IGD function 1 enable HVCO, 8, // 0xc7 - IGD HPLL VCO @@ -163,10 +164,23 @@ Field (GNVS, ByteAcc, NoLock, Preserve) NXD7, 32, // 0xe0 - IGD _DGS next DID7 NXD8, 32, // 0xe4 - IGD _DGS next DID8 + ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) + PAVP, 8, // 0xe9 - IGD PAVP data + Offset (0xeb), + OSCC, 8, // 0xeb - PCIe OSC control + NPCE, 8, // 0xec - native pcie support + PLFL, 8, // 0xed - platform flavor + BREV, 8, // 0xee - board revision + DPBM, 8, // 0xef - digital port b mode + DPCM, 8, // 0xf0 - digital port c mode + DPDM, 8, // 0xf1 - digital port d mode + ALFP, 8, // 0xf2 - active lfp + IMON, 8, // 0xf3 - current graphics turbo imon value + MMIO, 8, // 0xf4 - 64bit mmio support + /* ChromeOS specific */ - Offset (0xf0), + Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> - // 0xe8a - end } /* Set flag to enable USB charging in S3 */ |