diff options
author | Marc Jones <marc.jones@se-eng.com> | 2012-11-13 15:07:45 -0700 |
---|---|---|
committer | Marc Jones <marc.jones@se-eng.com> | 2013-03-09 00:09:37 +0100 |
commit | e7ae96f48834d57fd1a6c8940fa3f64b97520ed9 (patch) | |
tree | 34a5d2b6bb7bf08b82b5d1a8bf88c94294c704f7 /src/southbridge/intel/bd82x6x/acpi | |
parent | 4733c647bc64cef86f03efd64a145e4da6fef123 (diff) |
Add Intel Panther Point USB3 initialization
Add PEI updates and ACPI updates for supporting EHCI to XHCI
USB port support.
Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2519
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/acpi')
-rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 14 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pch.asl | 23 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/usb.asl | 69 |
3 files changed, 97 insertions, 9 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 2fe092d952..99edc317cf 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -136,6 +136,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE + /* XHCI */ + Offset (0xb2), + XHCI, 8, /* IGD OpRegion */ Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address @@ -223,6 +226,17 @@ Method (S3GD) Store (Zero, \S33G) } +/* Set XHCI Mode enable */ +Method (XHCE) +{ + Store (One, \XHCI) +} + +/* Set XHCI Mode disable */ +Method (XHCD) +{ + Store (Zero, \XHCI) +} External (\_TZ.THRM) External (\_TZ.SKIN) diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 8632ad849e..2f75fdc3f7 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -245,7 +245,7 @@ Scope(\) // PCI Express Ports 0:1c.x #include "pcie.asl" -// USB 0:1d.0 and 0:1a.0 +// USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0 #include "usb.asl" // LPC Bridge 0:1f.0 @@ -259,17 +259,22 @@ Scope(\) Method (_OSC, 4) { - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + /* Check for XHCI */ + If (LEqual (Arg0, ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) { - /* Let OS control everything */ - Return (Arg3) + Return (^XHC.POSC(Arg1, Arg2, Arg3)) } - Else + + /* Check for PCIe */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + /* Let OS control everything */ Return (Arg3) } + + /* Else Return Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl index cf3e6a049f..f19d3685ae 100644 --- a/src/southbridge/intel/bd82x6x/acpi/usb.asl +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -89,3 +89,72 @@ Device (EHC2) } } +Device (XHC) +{ + Name(_ADR, 0x00140000) + OperationRegion(XDEV, PCI_Config, 0, 256) + Field(XDEV, DWordAcc, NoLock, Preserve) + { + Offset(0xD0), + X2PR, 32, // XUSB2PR + PRM2, 32, // XUSB2PRM + SSEN, 32, // USB3_PSSEN + RPM3, 32, // USB3PRM + XPRT, 32, // XHCI Ports + } + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + Method(POSC,3,Serialized) + { + // Create DWord field from the Capabilities Buffer + CreateDWordField(Arg2,0,CDW1) + + // Check revision + If(LNotEqual(Arg1,One)) { + // Set unknown revision bit + Or(CDW1,0x8,CDW1) + } + + // Set failure if xHCI is disabled by coreboot + If(LEqual(XHCI, 0)) { + Or(CDW1,0x2,CDW1) + } + + // Query flag clear and xHCI in auto mode + If(LAnd(LNot(And(CDW1,0x1)),LOr(LEqual(XHCI ,2), LEqual(XHCI ,3)))) { + Store ("XHCI Switch", Debug) + Store(Zero, Local0) + And(XPRT, 0x3, Local0) + If(LOr(LEqual(Local0, 0), LEqual(Local0, 1))) { + Store(0xF, Local1) + } + ElseIf(LEqual(Local0, 2)) { + Store(0x3, Local1) + } + ElseIf(LEqual(Local0, 3)) { + Store(Zero, Local1) + } + And(RPM3, 0xFFFFFFF0, Local0) + Or(Local0, Local1, RPM3) + And(PRM2, 0xFFFFFFF0, Local0) + Or(Local0, Local1, PRM2) + And(SSEN, 0xFFFFFFF0, Local0) + Or(Local0, Local1, SSEN) + And(X2PR, 0xFFFFFFF0, Local0) + Or(Local0, Local1, X2PR) + } + Return(Arg2) + } + + // Leave USB ports on for to allow Wake from USB + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } +} |