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authorStefan Reinauer <stefan.reinauer@coreboot.org>2012-04-04 00:07:22 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-04-04 19:10:51 +0200
commit8e073829ec69ee89b3e91f4c040c96988084a526 (patch)
tree2e2b378ec66aa3ecd563b253726aae6e71db043a /src/southbridge/intel/bd82x6x/acpi/sata.asl
parentcb91e1525eb0b81f9bc2e24e3404d6a9efc1cce3 (diff)
Add support for Intel Panther Point PCH
Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/853 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/acpi/sata.asl')
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/sata.asl83
1 files changed, 83 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl
new file mode 100644
index 0000000000..e0c336ac5d
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel SATA Controller 0:1f.2
+
+// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily
+// pluggable
+
+Device (SATA)
+{
+ Name (_ADR, 0x001f0002)
+
+ Device (PRID)
+ {
+ Name (_ADR, 0)
+
+ // Get Timing Mode
+ Method (_GTM)
+ {
+ Name(PBUF, Buffer(20) {
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00 })
+
+ CreateDwordField (PBUF, 0, PIO0)
+ CreateDwordField (PBUF, 4, DMA0)
+ CreateDwordField (PBUF, 8, PIO1)
+ CreateDwordField (PBUF, 12, DMA1)
+ CreateDwordField (PBUF, 16, FLAG)
+
+ // TODO fill return structure
+
+ Return (PBUF)
+ }
+
+ // Set Timing Mode
+ Method (_STM, 3)
+ {
+ CreateDwordField (Arg0, 0, PIO0)
+ CreateDwordField (Arg0, 4, DMA0)
+ CreateDwordField (Arg0, 8, PIO1)
+ CreateDwordField (Arg0, 12, DMA1)
+ CreateDwordField (Arg0, 16, FLAG)
+
+ // TODO: Do the deed
+ }
+
+ Device (DSK0)
+ {
+ Name (_ADR, 0)
+ // TODO: _RMV ?
+ // TODO: _GTF ?
+ }
+
+ Device (DSK1)
+ {
+ Name (_ADR, 1)
+
+ // TODO: _RMV ?
+ // TODO: _GTF ?
+ }
+
+ }
+}
+