diff options
| author | Marc Jones <marc.jones@se-eng.com> | 2012-11-13 15:07:45 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2013-03-09 00:09:37 +0100 |
| commit | e7ae96f48834d57fd1a6c8940fa3f64b97520ed9 (patch) | |
| tree | 34a5d2b6bb7bf08b82b5d1a8bf88c94294c704f7 /src/southbridge/intel/bd82x6x/acpi/pch.asl | |
| parent | 4733c647bc64cef86f03efd64a145e4da6fef123 (diff) | |
Add Intel Panther Point USB3 initialization
Add PEI updates and ACPI updates for supporting EHCI to XHCI
USB port support.
Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2519
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/acpi/pch.asl')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pch.asl | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 8632ad849e..2f75fdc3f7 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -245,7 +245,7 @@ Scope(\) // PCI Express Ports 0:1c.x #include "pcie.asl" -// USB 0:1d.0 and 0:1a.0 +// USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0 #include "usb.asl" // LPC Bridge 0:1f.0 @@ -259,17 +259,22 @@ Scope(\) Method (_OSC, 4) { - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + /* Check for XHCI */ + If (LEqual (Arg0, ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) { - /* Let OS control everything */ - Return (Arg3) + Return (^XHC.POSC(Arg1, Arg2, Arg3)) } - Else + + /* Check for PCIe */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + /* Let OS control everything */ Return (Arg3) } + + /* Else Return Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } |