diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-04-27 09:55:45 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-01 21:21:19 +0200 |
| commit | c3230368849da3eaaffbd370fb80e344b5c266f0 (patch) | |
| tree | 5276115795bbc34135107723a01676e02d02abf8 /src/southbridge/intel/bd82x6x/acpi/pch.asl | |
| parent | 2c41c4027f50673826a6c0ec2f1b066e748f5c6d (diff) | |
Update PCIe Root Port _PRT to handle re-mapped functions
The chipset enforces static-defined interrupt swizzling on PCIe root
ports so if a port is remapped to a different function it needs to
still report the proper interrupt map to the OS instead of assuming
that function number is equivalent to root port number.
This change also includes an update to the PCH function disable
register which was incorrect for CPT/PPT and would cause unpredictable
behavior if used.
The kernel command line was changed to add 'nomsi' in order to force
PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure
that the mapping is correct.
LUMPY current:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
16: 41518 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k
19: 720 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
16: 38988 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k
19: 347 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0
Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/978
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/bd82x6x/acpi/pch.asl')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pch.asl | 32 |
1 files changed, 19 insertions, 13 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 3e6651da75..8632ad849e 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -211,26 +211,32 @@ Scope(\) , 5, HPTE, 1, // Address Enable Offset(0x3418), // FD (Function Disable) - , 2, // Reserved - SATD, 1, // SATA disable + , 1, // Reserved + PCID, 1, // PCI bridge disable + SA1D, 1, // SATA1 disable SMBD, 1, // SMBUS disable HDAD, 1, // Azalia disable - , 2, // Reserved - ILND, 1, // Internal LAN disable - US1D, 1, // UHCI #1 disable - US2D, 1, // UHCI #2 disable - US3D, 1, // UHCI #3 disable - US4D, 1, // UHCI #4 disable - , 2, // Reserved + , 8, // Reserved + EH2D, 1, // EHCI #2 disable LPBD, 1, // LPC bridge disable - EHCD, 1, // EHCI disable - Offset(0x341a), // FD Root Ports + EH1D, 1, // EHCI #1 disable RP1D, 1, // Root Port 1 disable RP2D, 1, // Root Port 2 disable RP3D, 1, // Root Port 3 disable - RP4D, 1 // Root Port 4 disable + RP4D, 1, // Root Port 4 disable + RP5D, 1, // Root Port 5 disable + RP6D, 1, // Root Port 6 disable + RP7D, 1, // Root Port 7 disable + RP8D, 1, // Root Port 8 disable + TTRD, 1, // Thermal sensor registers disable + SA2D, 1, // SATA2 disable + Offset(0x3428), // FD2 (Function Disable 2) + BDFD, 1, // Display BDF + ME1D, 1, // ME Interface 1 disable + ME2D, 1, // ME Interface 2 disable + IDRD, 1, // IDE redirect disable + KTCT, 1, // Keyboard Text redirect disable } - } // High Definition Audio (Azalia) 0:1b.0 |