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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-06-11 15:15:46 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 23:17:17 +0200 |
| commit | 998f3a27be2a16ae0bc1f193a805b680208d63ab (patch) | |
| tree | eab8d4c149630e72d4ff47e698883ddcbc92f1fc /src/southbridge/intel/bd82x6x/Makefile.inc | |
| parent | 49058c0adf348342ea23711f018997816da4056b (diff) | |
Cougar/Panther Point: Compile in ME7 and ME8 code at the same time
In the short term there might be devices with Sandy Bridge CPUs
on mainboards with Panther Point PCHes. While this configuration
option is perfectly valid, coreboot currently ties Sandy Bridge to
Cougar Point and Ivy Bridge to Panther Point. One occurence is in
the ME handling code.
To make coreboot most flexible, compile both ME handlers into
coreboot and decide at runtime which one to use.
Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1280
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index f086426aa5..11a6b08081 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -17,9 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -me-src-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += me.c -me-src-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += me_8.x.c - driver-y += pch.c driver-y += azalia.c driver-y += lpc.c @@ -27,7 +24,8 @@ driver-y += pci.c driver-y += pcie.c driver-y += sata.c driver-y += usb_ehci.c -driver-y += $(me-src-y) +driver-y += me.c +driver-y += me_8.x.c driver-y += smbus.c ramstage-y += me_status.c @@ -37,7 +35,7 @@ ramstage-y += watchdog.c ramstage-y += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c $(me-src-y) finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c |