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authorUwe Hermann <uwe@hermann-uwe.de>2010-12-09 18:09:14 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-12-09 18:09:14 +0000
commit42b1c43c4dad6a58f444e868b84c6bbd10009681 (patch)
treea1c380d769f64606f7405f3c770ce73770f71c4c /src/southbridge/broadcom
parentd6ecfdbc84298840ded02f5c4d009732786ed847 (diff)
Merge enable_rom.c files into bootblock.c files.
All southbridges using TINY_BOOTBLOCK have a bootblock.c files which simply includes an enable_rom.c files. As discussed on the mailing list, drop the enable_rom.c file by merging it into bootblock.c. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/broadcom')
-rw-r--r--src/southbridge/broadcom/bcm5785/bootblock.c20
-rw-r--r--src/southbridge/broadcom/bcm5785/enable_rom.c39
2 files changed, 19 insertions, 40 deletions
diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
index f51fcd0ff9..cadda53596 100644
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ b/src/southbridge/broadcom/bcm5785/bootblock.c
@@ -18,7 +18,25 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include "enable_rom.c"
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
+static void bcm5785_enable_rom(void)
+{
+ u8 byte;
+ device_t dev;
+
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
+ PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);
+
+ /* Set the 4MB enable bits. */
+ byte = pci_read_config8(dev, 0x41);
+ byte |= 0x0e;
+ pci_write_config8(dev, 0x41, byte);
+}
static void bootblock_southbridge_init(void)
{
diff --git a/src/southbridge/broadcom/bcm5785/enable_rom.c b/src/southbridge/broadcom/bcm5785/enable_rom.c
deleted file mode 100644
index 1cd28498b9..0000000000
--- a/src/southbridge/broadcom/bcm5785/enable_rom.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_ids.h>
-
-/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
-static void bcm5785_enable_rom(void)
-{
- u8 byte;
- device_t dev;
-
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS,
- PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0);
-
- /* Set the 4MB enable bits. */
- byte = pci_read_config8(dev, 0x41);
- byte |= 0x0e;
- pci_write_config8(dev, 0x41, byte);
-}