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authorZheng Bao <zheng.bao@amd.com>2009-06-04 01:57:03 +0000
committerZheng Bao <Zheng.Bao@amd.com>2009-06-04 01:57:03 +0000
commitd11bd003c6aa075fb1a9874a4eb23902edd96f06 (patch)
treea2967dfc28e24f1c86528aee9299baafde55e0c1 /src/southbridge/broadcom
parenta9c5ea08d07d343d32d4c083a232107bd84d8064 (diff)
This patch is about some noticable bugs which was made by no reason.
1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right? 2. In rs690_pcie.c, (1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment). In rpr 5.10.2, step 2, step 2.1 & step 2.6 (2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20, instead of PCIEIND_P: 0x20. In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/broadcom')
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