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author | Hannah Williams <hannah.williams@intel.com> | 2015-04-15 19:48:07 -0700 |
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committer | Nico Huber <nico.h@gmx.de> | 2017-08-07 20:03:02 +0000 |
commit | 2cfdde7346962e70768d745a7fb0ffbb52467934 (patch) | |
tree | 07c6e85eceb017f220925e95e65fc61ea2b7792a /src/southbridge/broadcom | |
parent | e88fa490a5248c0de6d51b07d4ede885f09637b6 (diff) |
soc/intel/braswell: Fix SPI write after FLOCKDN is set
The SPI controller initialization in finalize_chipset was failing
because FSP was setting FLOCKDN before finalize_chipset was called.
Hence move finalize_chipset to get called from BS_POST_DEVICE so that it is
called before FSP notify function-Ready To Boot state.
TEST: run flashrom with -VVV and observe supported opcodes and SPI
flash chip are reported correctly, and write/erase operations succeeed.
Original-Change-Id: I3c0297f3f2258cf77cf00db367f11ff4d1d9dc77
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I690fb4bf9e78bb58811c704179ba8b8f25ce95cc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/broadcom')
0 files changed, 0 insertions, 0 deletions