Various Debug Port southbridge implementation fixes / cosmetics.

 - Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of
   hardcoding their values.
   
 - SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE.
 
 - ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC.
 
 - s/uint32_t/u32/.
 
 - Cosmetics, whitespace, coding style fixes and added code comments.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 32 insertions, 22 deletions

diff --git a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
index 64b016e0d6..6a150aded0 100644
--- a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
@@ -17,25 +17,30 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdint.h>
 #include <usbdebug.h>
+#include <device/pci_def.h>
 
-#ifndef SB600_DEVN_BASE
-#define SB600_DEVN_BASE 0
-#endif
-
-#define EHCI_BAR_INDEX		0x10
-#define EHCI_BAR		0xFEF00000
-#define EHCI_DEBUG_OFFSET	0xE0
+#define EHCI_BAR		0xFEF00000	/* EHCI BAR address */
+#define EHCI_BAR_INDEX		0x10		/* TODO: DBUG_PRT[31:29] */
+#define EHCI_DEBUG_OFFSET	0xE0		/* Hardcoded to 0xE0 */
 
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
 {
+	/* TODO: Allow changing the physical USB port used as Debug Port. */
 }
 
-static void sb600_enable_usbdebug(u32 port)
+static void sb600_enable_usbdebug(unsigned int port)
 {
+	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
+
+	/* Select the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);
-	pci_write_config32(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5),
-			   EHCI_BAR_INDEX, EHCI_BAR);
-	pci_write_config8(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5), 0x04, 0x2);	/* mem space enable */
+
+	/* Set the EHCI BAR address. */
+	pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+
+	/* Enable access to the EHCI memory space registers. */
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 }
diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
index 06bcab77a3..0f40d862a7 100644
--- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
@@ -17,25 +17,30 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdint.h>
 #include <usbdebug.h>
+#include <device/pci_def.h>
 
-#ifndef SB700_DEVN_BASE
-#define SB700_DEVN_BASE 0
-#endif
-
-#define EHCI_BAR_INDEX		0x10
-#define EHCI_BAR		0xFEF00000
-#define EHCI_DEBUG_OFFSET	0xE0
+#define EHCI_BAR		0xFEF00000	/* EHCI BAR address */
+#define EHCI_BAR_INDEX		0x10		/* TODO: DBUG_PRT[31:29] */
+#define EHCI_DEBUG_OFFSET	0xE0		/* Hardcoded to 0xE0 */
 
 /* Required for successful build, but currently empty. */
 void set_debug_port(unsigned int port)
 {
+	/* TODO: Allow changing the physical USB port used as Debug Port. */
 }
 
-static void sb700_enable_usbdebug(u32 port)
+static void sb700_enable_usbdebug(unsigned int port)
 {
+	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
+
+	/* Select the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);
-	pci_write_config32(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5),
-			   EHCI_BAR_INDEX, EHCI_BAR);
-	pci_write_config8(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), 0x04, 0x2);	/* mem space enable */
+
+	/* Set the EHCI BAR address. */
+	pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+
+	/* Enable access to the EHCI memory space registers. */
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 }