diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-22 11:42:32 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-22 11:42:32 +0000 |
| commit | c02b4fc9db3c3c1e263027382697b566127f66bb (patch) | |
| tree | 11bd18488e360e5c1beeb9ccb852ef4489c3689a /src/southbridge/amd | |
| parent | 27852aba6787617ca5656995cbc7e8ef0a3ea22c (diff) | |
printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
43 files changed, 276 insertions, 278 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c index 67a789c08a..32e3808a98 100644 --- a/src/southbridge/amd/amd8111/amd8111_acpi.c +++ b/src/southbridge/amd/amd8111/amd8111_acpi.c @@ -79,7 +79,7 @@ static void acpi_init(struct device *dev) #if 0 uint16_t word; - printk_debug("ACPI: disabling NMI watchdog.. "); + printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. "); byte = pci_read_config8(dev, 0x49); pci_write_config8(dev, 0x49, byte | (1<<2)); @@ -91,13 +91,13 @@ static void acpi_init(struct device *dev) byte = pci_read_config8(dev, 0x48); pci_write_config8(dev, 0x48, byte | (1<<3)); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); - printk_debug("ACPI: Routing IRQ 12 to PS2 port.. "); + printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. "); word = pci_read_config16(dev, 0x46); pci_write_config16(dev, 0x46, word | (1<<9)); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif /* To enable the register 0xcf9 in the IO space @@ -119,7 +119,7 @@ static void acpi_init(struct device *dev) byte |= 0x40; } pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk_info("set power %s after power fail\n", on?"on":"off"); + printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); /* switch serial irq logic from quiet mode to continuous * mode for Winbond W83627HF Rev. 17 @@ -135,13 +135,13 @@ static void acpi_init(struct device *dev) outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); on = 8-on; - printk_debug("Throttling CPU %2d.%1.1d percent.\n", + printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on*12)+(on>>1),(on&1)*5); } #if CONFIG_GENERATE_ACPI_TABLES == 1 pm_base = pci_read_config16(dev, 0x58) & 0xff00; - printk_debug("pm_base: 0x%04x\n",pm_base); + printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base); #endif } diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/amd8111_ide.c index 6a1fd553b2..3b6f5a0a65 100644 --- a/src/southbridge/amd/amd8111/amd8111_ide.c +++ b/src/southbridge/amd/amd8111/amd8111_ide.c @@ -19,12 +19,12 @@ static void ide_init(struct device *dev) if (conf->ide1_enable) { /* Enable secondary ide interface */ word |= (1<<0); - printk_debug("IDE1 "); + printk(BIOS_DEBUG, "IDE1 "); } if (conf->ide0_enable) { /* Enable primary ide interface */ word |= (1<<1); - printk_debug("IDE0 "); + printk(BIOS_DEBUG, "IDE0 "); } word |= (1<<12); diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c index edb32c240c..85e217bb65 100644 --- a/src/southbridge/amd/amd8111/amd8111_lpc.c +++ b/src/southbridge/amd/amd8111/amd8111_lpc.c @@ -22,7 +22,7 @@ static void enable_hpet(struct device *dev) pci_write_config32(dev,0xa0, 0xfed00001); hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; - printk_debug("enabling HPET @0x%lx\n", hpet_address); + printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c index aa06253a46..8818b51b40 100644 --- a/src/southbridge/amd/amd8111/amd8111_nic.c +++ b/src/southbridge/amd/amd8111/amd8111_nic.c @@ -52,7 +52,7 @@ static void nic_init(struct device *dev) mmio = resource->base; /* Hard Reset PHY */ - printk_debug("Reseting PHY... "); + printk(BIOS_DEBUG, "Reseting PHY... "); if (conf->phy_lowreset) { write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { @@ -60,7 +60,7 @@ static void nic_init(struct device *dev) } mdelay(15); write32((mmio + CMD3), RESET_PHY); - printk_debug("Done\n"); + printk(BIOS_DEBUG, "Done\n"); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/amd/amd8111/amd8111_usb2.c b/src/southbridge/amd/amd8111/amd8111_usb2.c index 0156b6ac2f..3aa5211dd0 100644 --- a/src/southbridge/amd/amd8111/amd8111_usb2.c +++ b/src/southbridge/amd/amd8111/amd8111_usb2.c @@ -26,7 +26,7 @@ static void amd8111_usb2_enable(device_t dev) // Due to buggy USB2 we force it to disable. dev->enabled = 0; amd8111_enable(dev); - printk_debug("USB2 disabled.\n"); + printk(BIOS_DEBUG, "USB2 disabled.\n"); } static struct device_operations usb2_ops = { diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c index 29713a37c8..04930517e6 100644 --- a/src/southbridge/amd/amd8131/amd8131_bridge.c +++ b/src/southbridge/amd/amd8131/amd8131_bridge.c @@ -83,7 +83,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) } - printk_debug("%s AMD8131 PCI-X tuning\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s AMD8131 PCI-X tuning\n", dev_path(dev)); status = pci_read_config32(dev, cap + PCI_X_STATUS); orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD); @@ -170,7 +170,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) } } #if 0 - printk_debug("%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n", + printk(BIOS_DEBUG, "%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n", dev_path(dev), max_read, max_tran, sibs, sib_funcs, sib_funcs); #endif if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) { @@ -214,7 +214,7 @@ static unsigned int amd8131_scan_bus(struct bus *bus, info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS); /* Print the PCI-X bus speed */ - printk_debug("PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus)); + printk(BIOS_DEBUG, "PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus)); /* Examine the bus and find out how loaded it is */ @@ -260,7 +260,7 @@ static unsigned int amd8131_scan_bus(struct bus *bus, * implement relaxed ordering. Errata #58 */ for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) { - printk_spew("%s disabling relaxed ordering\n", + printk(BIOS_SPEW, "%s disabling relaxed ordering\n", bus_path(pbus)); pbus->disable_relaxed_ordering = 1; } diff --git a/src/southbridge/amd/amd8132/amd8132_bridge.c b/src/southbridge/amd/amd8132/amd8132_bridge.c index 8dc57d4510..2c18c5ebcb 100644 --- a/src/southbridge/amd/amd8132/amd8132_bridge.c +++ b/src/southbridge/amd/amd8132/amd8132_bridge.c @@ -107,7 +107,7 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr) /* How many siblings does this device have? */ sibs = info->master_devices - 1; - printk_debug("%s AMD8132 PCI-X tuning\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s AMD8132 PCI-X tuning\n", dev_path(dev)); status = pci_read_config32(dev, cap + PCI_X_STATUS); orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD); @@ -177,7 +177,7 @@ static unsigned int amd8132_scan_bus(struct bus *bus, info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS); /* Print the PCI-X bus speed */ - printk_debug("PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev); + printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev); /* Examine the bus and find out how loaded it is */ diff --git a/src/southbridge/amd/cs5530/cs5530_ide.c b/src/southbridge/amd/cs5530/cs5530_ide.c index 09906b78bc..a1fa2dc2c3 100644 --- a/src/southbridge/amd/cs5530/cs5530_ide.c +++ b/src/southbridge/amd/cs5530/cs5530_ide.c @@ -55,9 +55,9 @@ static void ide_init(struct device *dev) pci_write_config8(dev, DECODE_CONTROL_REG2, reg8); - printk_info("%s IDE interface %s\n", "Primary", + printk(BIOS_INFO, "%s IDE interface %s\n", "Primary", conf->ide0_enable ? "enabled" : "disabled"); - printk_info("%s IDE interface %s\n", "Secondary", + printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary", conf->ide1_enable ? "enabled" : "disabled"); } diff --git a/src/southbridge/amd/cs5530/cs5530_vga.c b/src/southbridge/amd/cs5530/cs5530_vga.c index 9347a081b8..2a2a8d8bdf 100644 --- a/src/southbridge/amd/cs5530/cs5530_vga.c +++ b/src/southbridge/amd/cs5530/cs5530_vga.c @@ -460,7 +460,7 @@ static void cs5530_vga_init(device_t dev) gx_base = GX_BASE; mode = modes[CONFIG_GX1_VIDEOMODE]; - printk_debug("Setting up video mode %dx%d with %d Hz clock\n", + printk(BIOS_DEBUG, "Setting up video mode %dx%d with %d Hz clock\n", mode->visible_pixel, mode->visible_lines, mode->pixel_clock); cs5530_set_clock_frequency(io_base, mode->pll_value); diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 17bd902e0b..6f203558e3 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -39,14 +39,14 @@ static void nvram_on(struct device *dev) *flash = 0xf0; - printk_debug("Flash device: MFGID %02x, DEVID %02x\n", id1, id2); + printk(BIOS_DEBUG, "Flash device: MFGID %02x, DEVID %02x\n", id1, id2); #endif } static void southbridge_init(struct device *dev) { - printk_spew("cs5535: %s\n", __func__); + printk(BIOS_SPEW, "cs5535: %s\n", __func__); nvram_on(dev); } @@ -56,17 +56,17 @@ static void dump_south(struct device *dev) int i, j; for(i=0; i<256; i+=16) { - printk_debug("0x%02x: ", i); + printk(BIOS_DEBUG, "0x%02x: ", i); for(j=0; j<16; j++) - printk_debug("%02x ", pci_read_config8(dev, i+j)); - printk_debug("\n"); + printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j)); + printk(BIOS_DEBUG, "\n"); } } */ static void southbridge_enable(struct device *dev) { - printk_spew("%s: dev is %p\n", __func__, dev); + printk(BIOS_SPEW, "%s: dev is %p\n", __func__, dev); } static void cs5535_read_resources(device_t dev) @@ -89,7 +89,7 @@ static void cs5535_read_resources(device_t dev) static void cs5535_pci_dev_enable_resources(device_t dev) { - printk_spew("cs5535.c: %s()\n", __func__); + printk(BIOS_SPEW, "cs5535.c: %s()\n", __func__); pci_dev_enable_resources(dev); enable_childrens_resources(dev); } diff --git a/src/southbridge/amd/cs5535/cs5535_ide.c b/src/southbridge/amd/cs5535/cs5535_ide.c index 30901672b7..b997ca2463 100644 --- a/src/southbridge/amd/cs5535/cs5535_ide.c +++ b/src/southbridge/amd/cs5535/cs5535_ide.c @@ -7,12 +7,12 @@ static void ide_init(struct device *dev) { - printk_spew("cs5535_ide: %s\n", __func__); + printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__); } static void ide_enable(struct device *dev) { - printk_spew("cs5535_ide: %s\n", __func__); + printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__); } static struct device_operations ide_ops = { diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index e974d399d1..f068006f75 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -155,10 +155,10 @@ static void ChipsetFlashSetup(void) int i; int numEnabled = 0; - printk_debug("ChipsetFlashSetup: Start\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup: Start\n"); for (i = 0; i < FlashInitTableLen; i++) { if (FlashInitTable[i].fType != FLASH_TYPE_NONE) { - printk_debug("Enable CS%d\n", i); + printk(BIOS_DEBUG, "Enable CS%d\n", i); /* we need to configure the memory/IO mask */ msr = rdmsr(FlashPort[i]); msr.hi = 0; /* start with the "enabled" bit clear */ @@ -171,14 +171,14 @@ static void ChipsetFlashSetup(void) else msr.hi &= ~0x00000004; msr.hi |= FlashInitTable[i].fMask; - printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo); wrmsr(FlashPort[i], msr); /* now write-enable the device */ msr = rdmsr(MDD_NORF_CNTRL); msr.lo |= (1 << i); - printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo); wrmsr(MDD_NORF_CNTRL, msr); @@ -187,7 +187,7 @@ static void ChipsetFlashSetup(void) } } - printk_debug("ChipsetFlashSetup: Finish\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup: Finish\n"); } @@ -566,7 +566,7 @@ void chipsetinit(void) } /* Flash BAR size Setup */ - printk_err("%sDoing ChipsetFlashSetup()\n", + printk(BIOS_ERR, "%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not "); if (sb->enable_ide_nand_flash == 1) ChipsetFlashSetup(); @@ -594,7 +594,7 @@ static void southbridge_init(struct device *dev) * unsigned short gpiobase = MDD_GPIO; */ - printk_err("cs5536: %s\n", __func__); + printk(BIOS_ERR, "cs5536: %s\n", __func__); setup_i8259(); lpc_init(sb); uarts_init(sb); @@ -606,7 +606,7 @@ static void southbridge_init(struct device *dev) (sb->enable_gpio_int_route >> 16)); } - printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __func__, + printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__, sb->enable_ide_nand_flash); if (sb->enable_ide_nand_flash == 1) { enable_ide_nand_flash_header(); @@ -616,7 +616,7 @@ static void southbridge_init(struct device *dev) /* disable unwanted virtual PCI devices */ for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) { - printk_debug("Disabling VPCI device: 0x%08X\n", + printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]); outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8); outl(0xDEADBEEF, 0xCFC); @@ -644,13 +644,13 @@ static void cs5536_read_resources(device_t dev) static void southbridge_enable(struct device *dev) { - printk_err("cs5536: %s: dev is %p\n", __func__, dev); + printk(BIOS_ERR, "cs5536: %s: dev is %p\n", __func__, dev); } static void cs5536_pci_dev_enable_resources(device_t dev) { - printk_err("cs5536: %s()\n", __func__); + printk(BIOS_ERR, "cs5536: %s()\n", __func__); pci_dev_enable_resources(dev); enable_childrens_resources(dev); } diff --git a/src/southbridge/amd/cs5536/cs5536_early_smbus.c b/src/southbridge/amd/cs5536/cs5536_early_smbus.c index e5a133e903..298feeed9b 100644 --- a/src/southbridge/amd/cs5536/cs5536_early_smbus.c +++ b/src/southbridge/amd/cs5536/cs5536_early_smbus.c @@ -53,7 +53,7 @@ static int smbus_wait(unsigned smbus_io_base) if ((val & SMB_STS_SDAST) != 0) break; if (val & (SMB_STS_BER | SMB_STS_NEGACK)) { - /*printk_debug("SMBUS WAIT ERROR %x\n", val); */ + /*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */ return SMBUS_ERROR; } } while (--loops); @@ -123,7 +123,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, /* check for bus conflict and NACK */ val = inb(smbus_io_base + SMB_STS); if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) { - /* printk_debug("SEND SLAVE ERROR (%x)\n", val); */ + /* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */ return SMBUS_ERROR; } return smbus_wait(smbus_io_base); diff --git a/src/southbridge/amd/cs5536/cs5536_ide.c b/src/southbridge/amd/cs5536/cs5536_ide.c index bbb6bb5bcd..4acf3ed61a 100644 --- a/src/southbridge/amd/cs5536/cs5536_ide.c +++ b/src/southbridge/amd/cs5536/cs5536_ide.c @@ -36,7 +36,7 @@ static void ide_init(struct device *dev) { uint32_t ide_cfg; - printk_spew("cs5536_ide: %s\n", __func__); + printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__); /* GPIO and IRQ setup are handled in the main chipset code. */ // Enable the channel and Post Write Buffer @@ -49,7 +49,7 @@ static void ide_init(struct device *dev) static void ide_enable(struct device *dev) { - printk_spew("cs5536_ide: %s\n", __func__); + printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__); } diff --git a/src/southbridge/amd/cs5536/cs5536_smbus2.h b/src/southbridge/amd/cs5536/cs5536_smbus2.h index 3b9e96c485..a470b3714c 100644 --- a/src/southbridge/amd/cs5536/cs5536_smbus2.h +++ b/src/southbridge/amd/cs5536/cs5536_smbus2.h @@ -78,7 +78,7 @@ static int smbus_wait(unsigned smbus_io_base) if ((val & SMB_STS_SDAST) != 0) break; if (val & (SMB_STS_BER | SMB_STS_NEGACK)) { - printk_debug("SMBUS WAIT ERROR %x\n", val); + printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); return SMBUS_ERROR; } } while (--loops); @@ -171,7 +171,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, /* check for bus conflict and NACK */ val = inb(smbus_io_base + SMB_STS); if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) { - printk_debug("SEND SLAVE ERROR (%x)\n", val); + printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); return SMBUS_ERROR; } return smbus_wait(smbus_io_base); @@ -250,7 +250,7 @@ static void _doread(unsigned smbus_io_base, unsigned char device, return; err: - printk_debug("SMBUS READ ERROR (%d): %d\n", index, ret); + printk(BIOS_DEBUG, "SMBUS READ ERROR (%d): %d\n", index, ret); } static unsigned char do_smbus_read_byte(unsigned smbus_io_base, @@ -300,7 +300,7 @@ static int _dowrite(unsigned smbus_io_base, unsigned char device, return 0; err: - printk_debug("SMBUS WRITE ERROR: %d\n", ret); + printk(BIOS_DEBUG, "SMBUS WRITE ERROR: %d\n", ret); return -1; } diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c index 40913b3388..caf838aacf 100644 --- a/src/southbridge/amd/rs690/rs690.c +++ b/src/southbridge/amd/rs690/rs690.c @@ -129,7 +129,7 @@ void rs690_enable(device_t dev) device_t nb_dev = 0, sb_dev = 0; int dev_ind; - printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); + printk(BIOS_INFO, "rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { @@ -147,7 +147,7 @@ void rs690_enable(device_t dev) dev_ind = dev->path.pci.devfn >> 3; switch (dev_ind) { case 0: /* bus0, dev0, fun0; */ - printk_info("Bus-0, Dev-0, Fun-0.\n"); + printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ config_gpp_core(nb_dev, sb_dev); rs690_gpp_sb_init(nb_dev, sb_dev, 8); @@ -159,11 +159,11 @@ void rs690_enable(device_t dev) break; case 1: /* bus0, dev1 */ - printk_info("Bus-0, Dev-1, Fun-0.\n"); + printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n"); break; case 2: /* bus0, dev2,3, two GFX */ case 3: - printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); + printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) @@ -173,7 +173,7 @@ void rs690_enable(device_t dev) case 5: case 6: case 7: - printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", + printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); @@ -181,7 +181,7 @@ void rs690_enable(device_t dev) rs690_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ - printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); + printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, (dev->enabled ? 1 : 0) << 6); if (dev->enabled) @@ -189,7 +189,7 @@ void rs690_enable(device_t dev) disable_pcie_bar3(nb_dev); break; default: - printk_debug("unknown dev: %s\n", dev_path(dev)); + printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); } } diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c index aa75a64f4f..026341394a 100644 --- a/src/southbridge/amd/rs690/rs690_cmn.c +++ b/src/southbridge/amd/rs690/rs690_cmn.c @@ -50,7 +50,7 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.pci.devfn << 12 | reg; @@ -63,7 +63,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.pci.devfn << 12 | reg_pos; @@ -253,7 +253,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) mdelay(40); udelay(200); lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ - printk_debug("PcieLinkTraining port=%x:lc current state=%x\n", + printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", port, lc_state); current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ @@ -274,7 +274,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); - printk_debug("PcieTrainPort reg=0x%x\n", reg); + printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ diff --git a/src/southbridge/amd/rs690/rs690_early_setup.c b/src/southbridge/amd/rs690/rs690_early_setup.c index d253f0d868..5afb7b57a3 100644 --- a/src/southbridge/amd/rs690/rs690_early_setup.c +++ b/src/southbridge/amd/rs690/rs690_early_setup.c @@ -133,23 +133,23 @@ static void get_cpu_rev() u32 eax, ebx, ecx, edx; __asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) :"0"(1)); - printk_info("get_cpu_rev EAX=0x%x.\n", eax); + printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax); if (eax <= 0xfff) - printk_info("CPU Rev is K8_Cx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Cx.\n"); else if (eax <= 0x10fff) - printk_info("CPU Rev is K8_Dx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Dx.\n"); else if (eax <= 0x20fff) - printk_info("CPU Rev is K8_Ex.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Ex.\n"); else if (eax <= 0x40fff) - printk_info("CPU Rev is K8_Fx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Fx.\n"); else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */ - printk_info("CPU Rev is K8_G1.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); else if (eax <= 0X60FF0) - printk_info("CPU Rev is K8_G0.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G0.\n"); else if (eax <= 0x100000) - printk_info("CPU Rev is K8_G1.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); else - printk_info("CPU Rev is K8_10.\n"); + printk(BIOS_INFO, "CPU Rev is K8_10.\n"); } static u8 get_nb_rev(device_t nb_dev) @@ -197,19 +197,19 @@ static void rs690_htinit() ************************/ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; - printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq); + printk(BIOS_SPEW, "rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq); rs690_f0 = PCI_DEV(0, 0, 0); reg8 = pci_read_config8(rs690_f0, 0x9c); - printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8); + printk(BIOS_SPEW, "rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8); /* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set. * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set. */ if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) { - printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n"); + printk(BIOS_INFO, "rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n"); reg8 |= 0x1; pci_write_config8(rs690_f0, 0x9c, reg8); } else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) { - printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n"); + printk(BIOS_INFO, "rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n"); reg8 &= ~0x1; pci_write_config8(rs690_f0, 0x9c, reg8); } @@ -234,7 +234,7 @@ static void k8_optimization() device_t k8_f0, k8_f2, k8_f3; msr_t msr; - printk_info("k8_optimization()\n"); + printk(BIOS_INFO, "k8_optimization()\n"); k8_f0 = PCI_DEV(0, 0x18, 0); k8_f2 = PCI_DEV(0, 0x18, 2); k8_f3 = PCI_DEV(0, 0x18, 3); @@ -425,7 +425,7 @@ static void rs690_por_htiu_index_init(device_t nb_dev) *****************************************/ static void rs690_por_init(device_t nb_dev) { - printk_info("rs690_por_init\n"); + printk(BIOS_INFO, "rs690_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */ rs690_por_pcicfg_init(nb_dev); @@ -463,19 +463,19 @@ static void rs690_before_pci_init() static void rs690_early_setup() { device_t nb_dev = PCI_DEV(0, 0, 0); - printk_info("rs690_early_setup()\n"); + printk(BIOS_INFO, "rs690_early_setup()\n"); /*ATINB_PrepareInit */ get_cpu_rev(); switch (get_nb_rev(nb_dev)) { /* PCIEMiscInit */ case 5: - printk_info("NB Revision is A11.\n"); + printk(BIOS_INFO, "NB Revision is A11.\n"); break; case 6: - printk_info("NB Revision is A12.\n"); + printk(BIOS_INFO, "NB Revision is A12.\n"); break; case 7: - printk_info("NB Revision is A21.\n"); + printk(BIOS_INFO, "NB Revision is A21.\n"); break; } diff --git a/src/southbridge/amd/rs690/rs690_gfx.c b/src/southbridge/amd/rs690/rs690_gfx.c index 3c87fa0447..7f76a057ac 100644 --- a/src/southbridge/amd/rs690/rs690_gfx.c +++ b/src/southbridge/amd/rs690/rs690_gfx.c @@ -45,7 +45,7 @@ static u32 clkind_read(device_t dev, u32 index) static void clkind_write(device_t dev, u32 index, u32 data) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; - /* printk_info("gfx bar 2 %02x\n", gfx_bar2); */ + /* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7; *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data; @@ -57,7 +57,7 @@ static void clkind_write(device_t dev, u32 index, u32 data) */ static void rs690_gfx_read_resources(device_t dev) { - printk_info("rs690_gfx_read_resources.\n"); + printk(BIOS_INFO, "rs690_gfx_read_resources.\n"); /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing. Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000, @@ -77,7 +77,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) (struct southbridge_amd_rs690_config *)dev->chip_info; deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n", + printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", deviceid, vendorid); pci_dev_init(dev); @@ -117,12 +117,12 @@ static void rs690_internal_gfx_enable(device_t dev) device_t k8_f0 = 0, k8_f2 = 0; device_t nb_dev = dev_find_slot(0, 0); - printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, + printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, nb_dev); /* set APERTURE_SIZE, 128M. */ l_dword = pci_read_config32(nb_dev, 0x8c); - printk_info("nb_dev, 0x8c=0x%x\n", l_dword); + printk(BIOS_INFO, "nb_dev, 0x8c=0x%x\n", l_dword); l_dword &= 0xffffff8f; pci_write_config32(nb_dev, 0x8c, l_dword); @@ -231,13 +231,13 @@ static void single_port_configuration(device_t nb_dev, device_t dev) struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_info("rs690_gfx_init single_port_configuration.\n"); + printk(BIOS_INFO, "rs690_gfx_init single_port_configuration.\n"); /* step 12 training, releases hold training for GFX port 0 (device 2) */ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0<<4); PcieReleasePortTraining(nb_dev, dev, 2); result = PcieTrainPort(nb_dev, dev, 2); - printk_info("rs690_gfx_init single_port_configuration step12.\n"); + printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step12.\n"); /* step 13 Power Down Control */ /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */ @@ -257,7 +257,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev) reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; - printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -274,11 +274,11 @@ static void single_port_configuration(device_t nb_dev, device_t dev) break; } } - printk_info("rs690_gfx_init single_port_configuration step13.\n"); + printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step13.\n"); /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19); - printk_info("rs690_gfx_init single_port_configuration step14.\n"); + printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step14.\n"); } /* step 15 ~ step 18 from rpr */ @@ -305,7 +305,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; - printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -335,7 +335,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; - printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -413,13 +413,13 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", + printk(BIOS_INFO, "rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* step 0, REFCLK_SEL, skip A11 revision */ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 9, cfg->gfx_dev2_dev3 ? 1 << 9 : 0 << 9); - printk_info("rs690_gfx_init step0.\n"); + printk(BIOS_INFO, "rs690_gfx_init step0.\n"); /* step 1, lane reversal (only need if CMOS option is enabled) */ if (cfg->gfx_lane_reversal) { @@ -427,13 +427,13 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) if (cfg->gfx_dual_slot) set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); } - printk_info("rs690_gfx_init step1.\n"); + printk(BIOS_INFO, "rs690_gfx_init step1.\n"); /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ /* AMD calls the configuration CrossFire */ if (cfg->gfx_dual_slot) set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk_info("rs690_gfx_init step2.\n"); + printk(BIOS_INFO, "rs690_gfx_init step2.\n"); /* step 2, TMDS, (only need if CMOS option is enabled) */ if (cfg->gfx_tmds) { @@ -461,7 +461,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) /* step 4.6 bring external GFX device out of reset, wait for 1ms */ mdelay(1); - printk_info("rs690_gfx_init step4.\n"); + printk(BIOS_INFO, "rs690_gfx_init step4.\n"); /* step 5 program PCIE memory mapped configuration space */ /* done by enable_pci_bar3() before */ @@ -508,7 +508,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2); } - printk_info("rs690_gfx_init step6.\n"); + printk(BIOS_INFO, "rs690_gfx_init step6.\n"); /* step 7 compliance state, (only need if CMOS option is enabled) */ /* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */ @@ -518,64 +518,64 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) /* release hold training for device 2. GFX initialization is done. */ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4); dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width); - printk_info("rs690_gfx_init step7.\n"); + printk(BIOS_INFO, "rs690_gfx_init step7.\n"); return; } /* step 8 common initialization */ /* step 8.1 sets RCB timeout to be 25ms */ set_pcie_enable_bits(dev, 0x70, 7 << 16, 3 << 16); - printk_info("rs690_gfx_init step8.1.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.1.\n"); /* step 8.2 disables slave ordering logic */ set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8); - printk_info("rs690_gfx_init step8.2.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.2.\n"); /* step 8.3 sets DMA payload size to 64 bytes */ set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10); - printk_info("rs690_gfx_init step8.3.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.3.\n"); /* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still * time out and go back to Detect Idle.*/ set_pcie_enable_bits(dev, 0x02, 1 << 14, 1 << 14); - printk_info("rs690_gfx_init step8.4.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.4.\n"); /* step 8.5 shortens the enumeration timer */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); - printk_info("rs690_gfx_init step8.5.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.5.\n"); /* step 8.6 blocks DMA traffic during C3 state */ set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); - printk_info("rs690_gfx_init step8.6.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.6.\n"); /* step 8.7 Do not gate the electrical idle form the PHY * step 8.8 Enables the escape from L1L23 */ set_pcie_enable_bits(dev, 0xa0, 3 << 30, 3 << 30); - printk_info("rs690_gfx_init step8.8.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.8.\n"); /* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM. * SLOT_IMPLEMENTED@PCIE_CAP */ reg16 = pci_read_config16(dev, 0x5a); reg16 |= 0x100; pci_write_config16(dev, 0x5a, reg16); - printk_info("rs690_gfx_init step8.9.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.9.\n"); /* step 8.10 Setting this register to 0x1 will hide the Advanced Error Rporting Capabilities in the PCIE Brider. * This will workaround several failures reported by the PCI Compliance test under Vista DTM. */ set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 31, 0 << 31); - printk_info("rs690_gfx_init step8.10.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.10.\n"); /* step 8.11 Sets REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off. */ set_pcie_enable_bits(nb_dev, 0x02, 1 << 0, 1 << 0); - printk_info("rs690_gfx_init step8.11.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.11.\n"); /* step 8.12 Sets REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent lc to go to from L0 to Rcv_L0s if L1 is armed. */ set_pcie_enable_bits(nb_dev, 0x02, 1 << 6, 1 << 6); - printk_info("rs690_gfx_init step8.12.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.12.\n"); /* step 8.13 Sets CMGOOD_OVERRIDE. */ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17); - printk_info("rs690_gfx_init step8.13.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.13.\n"); /* step 9 Enable TLP Flushing, for non-AMD GFX devices and Hot-Plug devices only. */ /* skip */ @@ -619,7 +619,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) dual_port_configuration(nb_dev, dev); break; default: - printk_info("Incorrect configuration of external gfx slot.\n"); + printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n"); break; } } diff --git a/src/southbridge/amd/rs690/rs690_ht.c b/src/southbridge/amd/rs690/rs690_ht.c index ef4b34296e..26824b5322 100644 --- a/src/southbridge/amd/rs690/rs690_ht.c +++ b/src/southbridge/amd/rs690/rs690_ht.c @@ -53,7 +53,7 @@ static void pcie_init(struct device *dev) /* Enable pci error detecting */ u32 dword; - printk_info("pcie_init in rs690_ht.c\n"); + printk(BIOS_INFO, "pcie_init in rs690_ht.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c index 91e6bb1066..ad2e871db4 100644 --- a/src/southbridge/amd/rs690/rs690_pcie.c +++ b/src/southbridge/amd/rs690/rs690_pcie.c @@ -110,7 +110,7 @@ static void pcie_init(struct device *dev) /* Enable pci error detecting */ u32 dword; - printk_debug("pcie_init in rs690_pcie.c\n"); + printk(BIOS_DEBUG, "pcie_init in rs690_pcie.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); @@ -168,7 +168,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) *****************************************************************/ void enable_pcie_bar3(device_t nb_dev) { - printk_debug("enable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "enable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); @@ -184,7 +184,7 @@ void enable_pcie_bar3(device_t nb_dev) *****************************************************************/ void disable_pcie_bar3(device_t nb_dev) { - printk_debug("disable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "disable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); @@ -206,7 +206,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) device_t sb_dev; struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); + printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); /* init GPP core */ set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, @@ -262,7 +262,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) PcieReleasePortTraining(nb_dev, dev, port); if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { u8 res = PcieTrainPort(nb_dev, dev, port); - printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res); + printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res); if (res) { AtiPcieCfg.PortDetect |= 1 << port; } diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index b7ec1154ce..471603f865 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -120,9 +120,9 @@ void rs780_nb_pci_table(device_t nb_dev) /* Program NB PCI table. */ temp16 = pci_read_config16(nb_dev, 0x04); - printk_debug("NB_PCI_REG04 = %x.\n", temp16); + printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16); temp32 = pci_read_config32(nb_dev, 0x84); - printk_debug("NB_PCI_REG84 = %x.\n", temp32); + printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32); pci_write_config8(nb_dev, 0x4c, 0x42); @@ -131,7 +131,7 @@ void rs780_nb_pci_table(device_t nb_dev) pci_write_config8(nb_dev, 0x4e, temp8); temp32 = pci_read_config32(nb_dev, 0x4c); - printk_debug("NB_PCI_REG4C = %x.\n", temp32); + printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32); /* disable GFX debug. */ temp8 = pci_read_config8(nb_dev, 0x8d); @@ -250,7 +250,7 @@ void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) /* Enable PCIe configuration space. */ set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28); - printk_info("GC is accessible from now on.\n"); + printk(BIOS_INFO, "GC is accessible from now on.\n"); } /*********************************************** @@ -272,7 +272,7 @@ void rs780_enable(device_t dev) device_t nb_dev = 0, sb_dev = 0; int dev_ind; - printk_info("rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); + printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { @@ -290,7 +290,7 @@ void rs780_enable(device_t dev) dev_ind = dev->path.pci.devfn >> 3; switch (dev_ind) { case 0: /* bus0, dev0, fun0; */ - printk_info("Bus-0, Dev-0, Fun-0.\n"); + printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ config_gpp_core(nb_dev, sb_dev); rs780_gpp_sb_init(nb_dev, sb_dev, 8); @@ -304,12 +304,12 @@ void rs780_enable(device_t dev) break; case 1: /* bus0, dev1, APC. */ - printk_info("Bus-0, Dev-1, Fun-0.\n"); + printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n"); rs780_nb_gfx_dev_table(nb_dev, dev); break; case 2: /* bus0, dev2,3, two GFX */ case 3: - printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); + printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) @@ -319,7 +319,7 @@ void rs780_enable(device_t dev) case 5: case 6: case 7: - printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", + printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); @@ -327,7 +327,7 @@ void rs780_enable(device_t dev) rs780_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ - printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); + printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, (dev->enabled ? 1 : 0) << 6); if (dev->enabled) @@ -336,7 +336,7 @@ void rs780_enable(device_t dev) break; case 9: /* bus 0, dev 9,10, GPP */ case 10: - printk_info("Bus-0, Dev-9, 10, Fun-0. enable=%d\n", + printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", dev->enabled); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), @@ -346,7 +346,7 @@ void rs780_enable(device_t dev) /* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ break; default: - printk_debug("unknown dev: %s\n", dev_path(dev)); + printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); } } diff --git a/src/southbridge/amd/rs780/rs780_cmn.c b/src/southbridge/amd/rs780/rs780_cmn.c index bf27794fc7..ab91074ad2 100644 --- a/src/southbridge/amd/rs780/rs780_cmn.c +++ b/src/southbridge/amd/rs780/rs780_cmn.c @@ -48,7 +48,7 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.pci.devfn << 12 | reg; @@ -61,7 +61,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.pci.devfn << 12 | reg_pos; @@ -271,7 +271,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) mdelay(40); udelay(200); lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ - printk_debug("PcieLinkTraining port=%x:lc current state=%x\n", + printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", port, lc_state); current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ @@ -297,7 +297,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg |= lane_mask << 8 | lane_mask; reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */ nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg); - printk_debug("link_width=%x, lane_mask=%x", + printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", current_link_width, lane_mask); set_pcie_reset(); mdelay(1); @@ -311,7 +311,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); - printk_debug("PcieTrainPort reg=0x%x\n", reg); + printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ diff --git a/src/southbridge/amd/rs780/rs780_early_setup.c b/src/southbridge/amd/rs780/rs780_early_setup.c index 5b9616f3ca..159d51f52e 100644 --- a/src/southbridge/amd/rs780/rs780_early_setup.c +++ b/src/southbridge/amd/rs780/rs780_early_setup.c @@ -147,25 +147,25 @@ static void get_cpu_rev() u32 eax; eax = cpuid_eax(1); - printk_info("get_cpu_rev EAX=0x%x.\n", eax); + printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax); if (eax <= 0xfff) - printk_info("CPU Rev is K8_Cx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Cx.\n"); else if (eax <= 0x10fff) - printk_info("CPU Rev is K8_Dx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Dx.\n"); else if (eax <= 0x20fff) - printk_info("CPU Rev is K8_Ex.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Ex.\n"); else if (eax <= 0x40fff) - printk_info("CPU Rev is K8_Fx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Fx.\n"); else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */ - printk_info("CPU Rev is K8_G1.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); else if (eax <= 0X60FF0) - printk_info("CPU Rev is K8_G0.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G0.\n"); else if (eax <= 0x100000) - printk_info("CPU Rev is K8_G1.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); else if (eax <= 0x100f00) - printk_info("CPU Rev is Fam 10.\n"); + printk(BIOS_INFO, "CPU Rev is Fam 10.\n"); else - printk_info("CPU Rev is K8_10.\n"); + printk(BIOS_INFO, "CPU Rev is K8_10.\n"); } static u8 is_famly10() @@ -246,7 +246,7 @@ static void rs780_htinit() ************************/ reg = pci_read_config32(cpu_f0, 0x88); cpu_ht_freq = (reg & 0xf00) >> 8; - printk_info("rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq); + printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq); rs780_f0 = PCI_DEV(0, 0, 0); //set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28); @@ -260,7 +260,7 @@ static void rs780_htinit() * So we check 6 only, it would be faster. */ if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) || (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) { - printk_info("rs780_htinit: HT1 mode\n"); + printk(BIOS_INFO, "rs780_htinit: HT1 mode\n"); /* HT1 mode, RPR 8.4.2 */ /* set IBIAS code */ @@ -268,7 +268,7 @@ static void rs780_htinit() /* Optimizes chipset HT transmitter drive strength */ set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1); } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { - printk_info("rs780_htinit: HT3 mode\n"); + printk(BIOS_INFO, "rs780_htinit: HT3 mode\n"); #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ /* HT3 mode, RPR 8.4.3 */ @@ -330,7 +330,7 @@ static void k8_optimization() device_t k8_f0, k8_f2, k8_f3; msr_t msr; - printk_info("k8_optimization()\n"); + printk(BIOS_INFO, "k8_optimization()\n"); k8_f0 = PCI_DEV(0, 0x18, 0); k8_f2 = PCI_DEV(0, 0x18, 2); k8_f3 = PCI_DEV(0, 0x18, 3); @@ -373,7 +373,7 @@ void fam10_optimization() msr_t msr; u32 val; - printk_info("fam10_optimization()\n"); + printk(BIOS_INFO, "fam10_optimization()\n"); cpu_f0 = PCI_DEV(0, 0x18, 0); cpu_f2 = PCI_DEV(0, 0x18, 2); @@ -612,7 +612,7 @@ static void rs780_por_htiu_index_init(device_t nb_dev) *****************************************/ static void rs780_por_init(device_t nb_dev) { - printk_info("rs780_por_init\n"); + printk(BIOS_INFO, "rs780_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */ rs780_por_pcicfg_init(nb_dev); @@ -642,20 +642,20 @@ static void rs780_before_pci_init() static void rs780_early_setup() { device_t nb_dev = PCI_DEV(0, 0, 0); - printk_info("rs780_early_setup()\n"); + printk(BIOS_INFO, "rs780_early_setup()\n"); get_cpu_rev(); - /* The printk_info(s) below cause the system unstable. */ + /* The printk(BIOS_INFO, s) below cause the system unstable. */ switch (get_nb_rev(nb_dev)) { case REV_RS780_A11: - /* printk_info("NB Revision is A11.\n"); */ + /* printk(BIOS_INFO, "NB Revision is A11.\n"); */ break; case REV_RS780_A12: - /* printk_info("NB Revision is A12.\n"); */ + /* printk(BIOS_INFO, "NB Revision is A12.\n"); */ break; case REV_RS780_A13: - /* printk_info("NB Revision is A13.\n"); */ + /* printk(BIOS_INFO, "NB Revision is A13.\n"); */ break; } diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c index aa46451410..808bcb175f 100644 --- a/src/southbridge/amd/rs780/rs780_gfx.c +++ b/src/southbridge/amd/rs780/rs780_gfx.c @@ -55,7 +55,7 @@ static u32 clkind_read(device_t dev, u32 index) static void clkind_write(device_t dev, u32 index, u32 data) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; - /* printk_info("gfx bar 2 %02x\n", gfx_bar2); */ + /* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7; *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data; @@ -67,7 +67,7 @@ static void clkind_write(device_t dev, u32 index, u32 data) */ static void rs780_gfx_read_resources(device_t dev) { - printk_info("rs780_gfx_read_resources.\n"); + printk(BIOS_INFO, "rs780_gfx_read_resources.\n"); /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing. Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000, @@ -189,7 +189,7 @@ CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) { tempdev = dev_find_slot(Bus, Dev << 3); Value = pci_read_config32(tempdev, 0); - printk_debug("Dev ID %x \n", Value); + printk(BIOS_DEBUG, "Dev ID %x \n", Value); if((Value & 0xffff) == 0x1102) {//Creative //Found Creative SB @@ -220,7 +220,7 @@ CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) } } } - printk_debug(" MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit); + printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit); if (MMIOStart < MMIOLimit) { Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO); @@ -310,7 +310,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n", + printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", deviceid, vendorid); command = pci_read_config16(dev, 0x04); @@ -420,7 +420,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.ulBootUpEngineClock = 500 * 100; /* set boot up GFX engine clock. */ vgainfo.ulReserved1[0] = 0; vgainfo.ulReserved1[1] = 0; value = pci_read_config32(k8_f2, 0x94); - printk_debug("MEMCLK = %x\n", value&0x7); + printk(BIOS_DEBUG, "MEMCLK = %x\n", value&0x7); vgainfo.ulBootUpUMAClock = 333 * 100; /* set boot up UMA memory clock. */ vgainfo.ulBootUpSidePortClock = 0; /* disable SP. */ vgainfo.ulMinSidePortClock = 0; /* disable SP. */ @@ -447,14 +447,14 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.usBootUpNBVoltage = 0x1a; value = pci_read_config32(nb_dev, 0xd0); - printk_debug("NB HT speed = %x.\n", value); + printk(BIOS_DEBUG, "NB HT speed = %x.\n", value); value = pci_read_config32(k8_f0, 0x88); - printk_debug("CPU HT speed = %x.\n", value); + printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value); vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */ /* HT width. */ value = pci_read_config32(nb_dev, 0xc8); - printk_debug("HT width = %x.\n", value); + printk(BIOS_DEBUG, "HT width = %x.\n", value); vgainfo.usMinHTLinkWidth = 16; vgainfo.usMaxHTLinkWidth = 16; vgainfo.usUMASyncStartDelay = 322; @@ -585,10 +585,10 @@ static void rs780_internal_gfx_enable(device_t dev) u32 FB_Start, FB_End; #endif - printk_info("rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); + printk(BIOS_INFO, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); sysmem = rdmsr(0xc001001a); - printk_info("sysmem = %x_%x\n", sysmem.hi, sysmem.lo); + printk(BIOS_INFO, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo); /* The system top memory in 780. */ pci_write_config32(nb_dev, 0x90, sysmem.lo); @@ -826,12 +826,12 @@ static void single_port_configuration(device_t nb_dev, device_t dev) struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk_info("rs780_gfx_init single_port_configuration.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration.\n"); /* step 12 training, releases hold training for GFX port 0 (device 2) */ PcieReleasePortTraining(nb_dev, dev, 2); result = PcieTrainPort(nb_dev, dev, 2); - printk_info("rs780_gfx_init single_port_configuration step12.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step12.\n"); /* step 13 Power Down Control */ /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */ @@ -851,7 +851,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev) set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1); reg32 = nbpcie_p_read_index(dev, 0x29); width = reg32 & 0xFF; - printk_debug("GFX Inactive Lanes = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -868,11 +868,11 @@ static void single_port_configuration(device_t nb_dev, device_t dev) break; } } - printk_info("rs780_gfx_init single_port_configuration step13.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step13.\n"); /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); - printk_info("rs780_gfx_init single_port_configuration step14.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step14.\n"); } static void dual_port_configuration(device_t nb_dev, device_t dev) @@ -905,7 +905,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) } else { /* step 16.b Link Training was successful */ reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; - printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -983,7 +983,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk_info("rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", + printk(BIOS_INFO, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* GFX Core Initialization */ @@ -995,13 +995,13 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) if (cfg->gfx_dual_slot) set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); } - printk_info("rs780_gfx_init step1.\n"); + printk(BIOS_INFO, "rs780_gfx_init step1.\n"); /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ /* AMD calls the configuration CrossFire */ if (cfg->gfx_dual_slot) set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk_info("rs780_gfx_init step2.\n"); + printk(BIOS_INFO, "rs780_gfx_init step2.\n"); /* step 2, TMDS, (only need if CMOS option is enabled) */ if (cfg->gfx_tmds) { @@ -1020,7 +1020,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, 1 << 6 | 1 << 8 | 1 << 10); reg32 = nbmisc_read_index(nb_dev, 0x28); - printk_info("misc 28 = %x\n", reg32); + printk(BIOS_INFO, "misc 28 = %x\n", reg32); /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31); @@ -1038,7 +1038,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, 0); reg32 = nbmisc_read_index(nb_dev, 0x28); - printk_info("misc 28 = %x\n", reg32); + printk(BIOS_INFO, "misc 28 = %x\n", reg32); /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31); @@ -1079,7 +1079,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* release hold training for device 2. GFX initialization is done. */ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4); dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width); - printk_info("rs780_gfx_init step7.\n"); + printk(BIOS_INFO, "rs780_gfx_init step7.\n"); return; } @@ -1087,11 +1087,11 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* 5.9.12.1 sets RCB timeout to be 25ms */ /* 5.9.12.2. RCB Cpl timeout on link down. */ set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19); - printk_info("rs780_gfx_init step5.9.12.1.\n"); + printk(BIOS_INFO, "rs780_gfx_init step5.9.12.1.\n"); /* step 5.9.12.3 disables slave ordering logic */ set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8); - printk_info("rs780_gfx_init step5.9.12.3.\n"); + printk(BIOS_INFO, "rs780_gfx_init step5.9.12.3.\n"); /* step 5.9.12.4 sets DMA payload size to 64 bytes */ set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10); @@ -1113,7 +1113,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17); - printk_info("rs780_gfx_init step5.9.12.9.\n"); + printk(BIOS_INFO, "rs780_gfx_init step5.9.12.9.\n"); /* 5.9.12.10 Sets the timer in Config state from 20us to */ /* 5.9.12.11 De-asserts RX_EN in L0s. */ @@ -1188,7 +1188,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) dual_port_configuration(nb_dev, dev); break; default: - printk_info("Incorrect configuration of external gfx slot.\n"); + printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n"); break; } } diff --git a/src/southbridge/amd/rs780/rs780_ht.c b/src/southbridge/amd/rs780/rs780_ht.c index b3fa05a529..03d4f84645 100644 --- a/src/southbridge/amd/rs780/rs780_ht.c +++ b/src/southbridge/amd/rs780/rs780_ht.c @@ -53,7 +53,7 @@ static void pcie_init(struct device *dev) /* Enable pci error detecting */ u32 dword; - printk_info("pcie_init in rs780_ht.c\n"); + printk(BIOS_INFO, "pcie_init in rs780_ht.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); diff --git a/src/southbridge/amd/rs780/rs780_pcie.c b/src/southbridge/amd/rs780/rs780_pcie.c index b778af3aa6..186266b8f1 100644 --- a/src/southbridge/amd/rs780/rs780_pcie.c +++ b/src/southbridge/amd/rs780/rs780_pcie.c @@ -106,7 +106,7 @@ static void pcie_init(struct device *dev) /* Enable pci error detecting */ u32 dword; - printk_debug("pcie_init in rs780_pcie.c\n"); + printk(BIOS_DEBUG, "pcie_init in rs780_pcie.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); @@ -216,7 +216,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) *****************************************************************/ void enable_pcie_bar3(device_t nb_dev) { - printk_debug("enable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "enable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); @@ -232,7 +232,7 @@ void enable_pcie_bar3(device_t nb_dev) *****************************************************************/ void disable_pcie_bar3(device_t nb_dev) { - printk_debug("disable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "disable_pcie_bar3()\n"); pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); @@ -255,7 +255,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) u32 gfx_gpp_sb_sel; struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port); + printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port); gfx_gpp_sb_sel = port >= 4 && port <= 8 ? PCIE_CORE_INDEX_GPPSB : /* 4,5,6,7,8 */ @@ -369,7 +369,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) PcieReleasePortTraining(nb_dev, dev, port); if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { u8 res = PcieTrainPort(nb_dev, dev, port); - printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res); + printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res); if (res) { AtiPcieCfg.PortDetect |= 1 << port; } diff --git a/src/southbridge/amd/sb600/sb600.c b/src/southbridge/amd/sb600/sb600.c index 1e34786b77..d9b3dcc9e4 100644 --- a/src/southbridge/amd/sb600/sb600.c +++ b/src/southbridge/amd/sb600/sb600.c @@ -118,7 +118,7 @@ void sb600_enable(device_t dev) u32 devfn; - printk_debug("sb600_enable()\n"); + printk(BIOS_DEBUG, "sb600_enable()\n"); /* * 0:12.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 @@ -220,7 +220,7 @@ void sb600_enable(device_t dev) index += 32 * 4; break; default: - printk_debug("unknown dev: %s deviceid=%4x\n", dev_path(dev), + printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev), deviceid); } } diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c index 29c215adba..b7581ec352 100644 --- a/src/southbridge/amd/sb600/sb600_early_setup.c +++ b/src/southbridge/amd/sb600/sb600_early_setup.c @@ -284,16 +284,16 @@ static void sb600_devices_por_init(void) device_t dev; u8 byte; - printk_info("sb600_devices_por_init()\n"); + printk(BIOS_INFO, "sb600_devices_por_init()\n"); /* SMBus Device, BDF:0-20-0 */ - printk_info("sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n"); + printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); /* NOT REACHED */ } - printk_info("SMBus controller enabled, sb revision is 0x%x\r\n", + printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n", get_sb600_revision()); /* sbPorAtStartOfTblCfg */ @@ -372,7 +372,7 @@ static void sb600_devices_por_init(void) outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); /* IDE Device, BDF:0-20-1 */ - printk_info("sb600_devices_por_init(): IDE Device, BDF:0-20-1\n"); + printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0); /* Disable prefetch */ byte = pci_read_config8(dev, 0x63); @@ -380,7 +380,7 @@ static void sb600_devices_por_init(void) pci_write_config8(dev, 0x63, byte); /* LPC Device, BDF:0-20-3 */ - printk_info("sb600_devices_por_init(): LPC Device, BDF:0-20-3\n"); + printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0); /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); @@ -417,7 +417,7 @@ static void sb600_devices_por_init(void) /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, * TODO: I don't know what are their mean? */ - printk_info("sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); + printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* I don't know why CIM tried to write into a read-only reg! */ /*pci_write_config8(dev, 0x0c, 0x20) */ ; @@ -448,7 +448,7 @@ static void sb600_devices_por_init(void) pci_write_config8(dev, 0x50, 0x01); /* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */ - printk_info("sb600_devices_por_init(): SATA Device, BDF:0-18-0\n"); + printk(BIOS_INFO, "sb600_devices_por_init(): SATA Device, BDF:0-18-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0); /*PHY Global Control, we are using A14. @@ -479,7 +479,7 @@ static void sb600_pmio_por_init(void) { u8 byte; - printk_info("sb600_pmio_por_init()\n"); + printk(BIOS_INFO, "sb600_pmio_por_init()\n"); /* K8KbRstEn, KB_RST# control for K8 system. */ byte = pmio_read(0x66); byte |= 0x20; @@ -676,7 +676,7 @@ static void sb600_before_pci_init(void) */ static void sb600_early_setup(void) { - printk_info("sb600_early_setup()\n"); + printk(BIOS_INFO, "sb600_early_setup()\n"); sb600_por_init(); } diff --git a/src/southbridge/amd/sb600/sb600_hda.c b/src/southbridge/amd/sb600/sb600_hda.c index 95e3744db5..3ba1fe910e 100644 --- a/src/southbridge/amd/sb600/sb600_hda.c +++ b/src/southbridge/amd/sb600/sb600_hda.c @@ -86,7 +86,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ set_bits(base + 0x08, 1, 0); - printk_debug("No codec!\n"); + printk(BIOS_DEBUG, "No codec!\n"); return 0; } @@ -156,9 +156,9 @@ static u32 find_verb(u32 viddid, u32 ** verb) device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2)); struct southbridge_amd_sb600_config *cfg = (struct southbridge_amd_sb600_config *)azalia_dev->chip_info; - printk_debug("Dev=%s\n", dev_path(azalia_dev)); - printk_debug("Default viddid=%x\n", cfg->hda_viddid); - printk_debug("Reading viddid=%x\n", viddid); + printk(BIOS_DEBUG, "Dev=%s\n", dev_path(azalia_dev)); + printk(BIOS_DEBUG, "Default viddid=%x\n", cfg->hda_viddid); + printk(BIOS_DEBUG, "Reading viddid=%x\n", viddid); if (!cfg) return 0; if (viddid != cfg->hda_viddid) @@ -232,15 +232,15 @@ static void codec_init(u32 base, int addr) dword = read32(base + 0x64); /* 2 */ - printk_debug("codec viddid: %08x\n", dword); + printk(BIOS_DEBUG, "codec viddid: %08x\n", dword); verb_size = find_verb(dword, &verb); if (!verb_size) { - printk_debug("No verb!\n"); + printk(BIOS_DEBUG, "No verb!\n"); return; } - printk_debug("verb_size: %d\n", verb_size); + printk(BIOS_DEBUG, "verb_size: %d\n", verb_size); /* 3 */ for (i = 0; i < verb_size; i++) { if (wait_for_ready(base) == -1) @@ -251,7 +251,7 @@ static void codec_init(u32 base, int addr) if (wait_for_valid(base) == -1) return; } - printk_debug("verb loaded!\n"); + printk(BIOS_DEBUG, "verb loaded!\n"); } static void codecs_init(u32 base, u32 codec_mask) @@ -302,11 +302,11 @@ static void hda_init(struct device *dev) return; base = ((u32)res->base); - printk_debug("base = 0x%x\n", base); + printk(BIOS_DEBUG, "base = 0x%x\n", base); codec_mask = codec_detect(base); if (codec_mask) { - printk_debug("codec_mask = %02x\n", codec_mask); + printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } } diff --git a/src/southbridge/amd/sb600/sb600_lpc.c b/src/southbridge/amd/sb600/sb600_lpc.c index a79cef9cf4..1f3253f55b 100644 --- a/src/southbridge/amd/sb600/sb600_lpc.c +++ b/src/southbridge/amd/sb600/sb600_lpc.c @@ -130,8 +130,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) continue; base = res->base; end = resource_end(res); - printk_debug - ("sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n", + printk(BIOS_DEBUG, "sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n", dev_path(child), base, end); switch (base) { case 0x60: /* KB */ diff --git a/src/southbridge/amd/sb600/sb600_sata.c b/src/southbridge/amd/sb600/sb600_sata.c index 251f5ad2f0..0feebac92f 100644 --- a/src/southbridge/amd/sb600/sb600_sata.c +++ b/src/southbridge/amd/sb600/sb600_sata.c @@ -35,22 +35,22 @@ static int sata_drive_detect(int portnum, u16 iobar) while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7), (byte != (0xA0 + 0x10 * (portnum % 2))) || ((byte2 & 0x88) != 0)) { - printk_spew("0x6=%x, 0x7=%x\n", byte, byte2); + printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); if (byte != (0xA0 + 0x10 * (portnum % 2))) { /* This will happen at the first iteration of this loop * if the first SATA port is unpopulated and the * second SATA port is poulated. */ - printk_debug("drive no longer selected after %i ms, " + printk(BIOS_DEBUG, "drive no longer selected after %i ms, " "retrying init\n", i * 10); return 1; } else - printk_spew("drive detection not yet completed, " + printk(BIOS_SPEW, "drive detection not yet completed, " "waiting...\n"); mdelay(10); i++; } - printk_spew("drive detection done after %i ms\n", i * 10); + printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10); return 0; } @@ -91,12 +91,12 @@ static void sata_init(struct device *dev) sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3; sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; - printk_spew("sata_bar0=%x\n", sata_bar0); /* 3030 */ - printk_spew("sata_bar1=%x\n", sata_bar1); /* 3070 */ - printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ - printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ - printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ + printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */ + printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */ + printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */ + printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */ + printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ + printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */ /* Program the 2C to 0x43801002 */ dword = 0x43801002; @@ -173,13 +173,13 @@ static void sata_init(struct device *dev) for (i = 0; i < 4; i++) { byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk_spew("SATA port %i status = %x\n", i, byte); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; if( byte == 0x1 ) { /* If the drive status is 0x1 then we see it but we aren't talking to it. */ /* Try to do something about it. */ - printk_spew("SATA device detected but not talking. Trying lower speed.\n"); + printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); /* Read in Port-N Serial ATA Control Register */ byte = read8(sata_bar5 + 0x12C + 0x80 * i); @@ -200,7 +200,7 @@ static void sata_init(struct device *dev) /* Reread status */ byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk_spew("SATA port %i status = %x\n", i, byte); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; } @@ -209,13 +209,13 @@ static void sata_init(struct device *dev) if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2)) break; } - printk_debug("%s %s device is %sready after %i tries\n", + printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", (j == 10) ? "not " : "", (j == 10) ? j : j + 1); } else { - printk_debug("No %s %s SATA drive on Slot%i\n", + printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", i); } @@ -240,7 +240,7 @@ static void sata_init(struct device *dev) /* word = pm_ioread(0x28); */ /* byte = pm_ioread(0x29); */ /* word |= byte<<8; */ - /* printk_debug("AcpiGpe0Blk addr = %x\n", word); */ + /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */ /* write32(word, 0x80000000); */ } diff --git a/src/southbridge/amd/sb600/sb600_sm.c b/src/southbridge/amd/sb600/sb600_sm.c index 8e275291ba..6a18bfeea5 100644 --- a/src/southbridge/amd/sb600/sb600_sm.c +++ b/src/southbridge/amd/sb600/sb600_sm.c @@ -54,7 +54,7 @@ static void sm_init(device_t dev) u32 on; u32 nmi_option; - printk_info("sm_init().\n"); + printk(BIOS_INFO, "sm_init().\n"); ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */ /* Don't rename APIC ID */ @@ -98,7 +98,7 @@ static void sm_init(device_t dev) } byte |= 1 << 2; pm_iowrite(0x74, byte); - printk_info("set power %s after power fail\n", on ? "on" : "off"); + printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); /* sb600 rpr:2.3.3: */ byte = pm_ioread(0x9A); @@ -154,10 +154,10 @@ static void sm_init(device_t dev) get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ - printk_info("++++++++++set NMI+++++\n"); + printk(BIOS_INFO, "++++++++++set NMI+++++\n"); } else { byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */ - printk_info("++++++++++no set NMI+++++\n"); + printk(BIOS_INFO, "++++++++++no set NMI+++++\n"); } byte &= ~(1 << 7); if (byte != byte_old) { @@ -197,9 +197,9 @@ static void sm_init(device_t dev) /* 3.12: Enabling AB and BIF Clock Gating */ abcfg_reg(0x10054, 0xFFFF0000, 0x1040000); abcfg_reg(0x54, 0xFF << 16, 4 << 16); - printk_info("3.11, ABCFG:0x54\n"); + printk(BIOS_INFO, "3.11, ABCFG:0x54\n"); abcfg_reg(0x54, 1 << 24, 1 << 24); - printk_info("3.12, ABCFG:0x54\n"); + printk(BIOS_INFO, "3.12, ABCFG:0x54\n"); abcfg_reg(0x98, 0x0000FF00, 0x00004700); /* 3.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */ @@ -211,7 +211,7 @@ static void sm_init(device_t dev) abcfg_reg(0x10098, 0xFFFFFFFF, 0x4000); abcfg_reg(0x04, 0xFFFFFFFF, 0x6); - printk_info("sm_init() end\n"); + printk(BIOS_INFO, "sm_init() end\n"); /* Enable NbSb virtual channel */ axcfg_reg(0x114, 0x3f << 1, 0 << 1); diff --git a/src/southbridge/amd/sb600/sb600_smbus.c b/src/southbridge/amd/sb600/sb600_smbus.c index df7ec56c3e..9e14930b09 100644 --- a/src/southbridge/amd/sb600/sb600_smbus.c +++ b/src/southbridge/amd/sb600/sb600_smbus.c @@ -188,7 +188,7 @@ static void alink_ab_indx(u32 reg_space, u32 reg_addr, tmp &= ~mask; tmp |= val; - /* printk_debug("about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */ + /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */ outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl(tmp, AB_DATA); } diff --git a/src/southbridge/amd/sb600/sb600_usb.c b/src/southbridge/amd/sb600/sb600_usb.c index 134e12560e..b6e1fbec6b 100644 --- a/src/southbridge/amd/sb600/sb600_usb.c +++ b/src/southbridge/amd/sb600/sb600_usb.c @@ -94,7 +94,7 @@ static void usb_init2(struct device *dev) /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; - printk_info("usb2_bar0=0x%x\n", usb2_bar0); + printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0); /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index 4bbde6dba2..39ae3a6b34 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -118,7 +118,7 @@ void sb700_enable(device_t dev) u32 devfn; - printk_debug("sb700_enable()\n"); + printk(BIOS_DEBUG, "sb700_enable()\n"); /* * 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 @@ -221,7 +221,7 @@ void sb700_enable(device_t dev) index = 4; break; default: - printk_debug("unknown dev: %s deviceid=%4x\n", dev_path(dev), + printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev), deviceid); } } diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c index a063c70cf9..3777bd6288 100644 --- a/src/southbridge/amd/sb700/sb700_early_setup.c +++ b/src/southbridge/amd/sb700/sb700_early_setup.c @@ -300,16 +300,16 @@ static void sb700_devices_por_init(void) device_t dev; u8 byte; - printk_info("sb700_devices_por_init()\n"); + printk(BIOS_INFO, "sb700_devices_por_init()\n"); /* SMBus Device, BDF:0-20-0 */ - printk_info("sb700_devices_por_init(): SMBus Device, BDF:0-20-0\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): SMBus Device, BDF:0-20-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); /* NOT REACHED */ } - printk_info("SMBus controller enabled, sb revision is A%x\r\n", + printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\r\n", set_sb700_revision()); /* sbPorAtStartOfTblCfg */ @@ -378,7 +378,7 @@ static void sb700_devices_por_init(void) outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); /* IDE Device, BDF:0-20-1 */ - printk_info("sb700_devices_por_init(): IDE Device, BDF:0-20-1\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): IDE Device, BDF:0-20-1\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0); /* Disable prefetch */ byte = pci_read_config8(dev, 0x63); @@ -386,7 +386,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x63, byte); /* LPC Device, BDF:0-20-3 */ - printk_info("sb700_devices_por_init(): LPC Device, BDF:0-20-3\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); @@ -423,7 +423,7 @@ static void sb700_devices_por_init(void) /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, */ - printk_info("sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* Arbiter enable. */ @@ -440,7 +440,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x50, 0x01); /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ - printk_info("sb700_devices_por_init(): SATA Device, BDF:0-18-0\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-18-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0); /*PHY Global Control*/ @@ -457,7 +457,7 @@ static void sb700_pmio_por_init(void) { u8 byte; - printk_info("sb700_pmio_por_init()\n"); + printk(BIOS_INFO, "sb700_pmio_por_init()\n"); /* K8KbRstEn, KB_RST# control for K8 system. */ byte = pmio_read(0x66); byte |= 0x20; @@ -602,7 +602,7 @@ static void sb700_before_pci_init(void) */ static void sb700_early_setup(void) { - printk_info("sb700_early_setup()\n"); + printk(BIOS_INFO, "sb700_early_setup()\n"); sb700_por_init(); } diff --git a/src/southbridge/amd/sb700/sb700_hda.c b/src/southbridge/amd/sb700/sb700_hda.c index 2f55c944c7..af1361692a 100644 --- a/src/southbridge/amd/sb700/sb700_hda.c +++ b/src/southbridge/amd/sb700/sb700_hda.c @@ -86,7 +86,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ set_bits(base + 0x08, 1, 0); - printk_debug("No codec!\n"); + printk(BIOS_DEBUG, "No codec!\n"); return 0; } @@ -150,7 +150,7 @@ static void codec_init(u32 base, int addr) dword = read32(base + 0x64); /* 2 */ - printk_debug("%x(th) codec viddid: %08x\n", addr, dword); + printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword); } static void codecs_init(u32 base, u32 codec_mask) @@ -203,11 +203,11 @@ static void hda_init(struct device *dev) return; base = (u32)res->base; - printk_debug("base = 0x%x\n", base); + printk(BIOS_DEBUG, "base = 0x%x\n", base); codec_mask = codec_detect(base); if (codec_mask) { - printk_debug("codec_mask = %02x\n", codec_mask); + printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } } diff --git a/src/southbridge/amd/sb700/sb700_lpc.c b/src/southbridge/amd/sb700/sb700_lpc.c index b6d7818160..3bc160827d 100644 --- a/src/southbridge/amd/sb700/sb700_lpc.c +++ b/src/southbridge/amd/sb700/sb700_lpc.c @@ -143,8 +143,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) continue; base = res->base; end = resource_end(res); - printk_debug - ("sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", + printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", dev_path(child), base, end); switch (base) { case 0x60: /* KB */ diff --git a/src/southbridge/amd/sb700/sb700_sata.c b/src/southbridge/amd/sb700/sb700_sata.c index cd5084e745..48c192c95d 100644 --- a/src/southbridge/amd/sb700/sb700_sata.c +++ b/src/southbridge/amd/sb700/sb700_sata.c @@ -34,22 +34,22 @@ int sata_drive_detect(int portnum, u16 iobar) while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7), (byte != (0xA0 + 0x10 * (portnum % 2))) || ((byte2 & 0x88) != 0)) { - printk_spew("0x6=%x, 0x7=%x\n", byte, byte2); + printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); if (byte != (0xA0 + 0x10 * (portnum % 2))) { /* This will happen at the first iteration of this loop * if the first SATA port is unpopulated and the * second SATA port is poulated. */ - printk_debug("drive no longer selected after %i ms, " + printk(BIOS_DEBUG, "drive no longer selected after %i ms, " "retrying init\n", i * 10); return 1; } else - printk_spew("drive detection not yet completed, " + printk(BIOS_SPEW, "drive detection not yet completed, " "waiting...\n"); mdelay(10); i++; } - printk_spew("drive detection done after %i ms\n", i * 10); + printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10); return 0; } @@ -96,12 +96,12 @@ static void sata_init(struct device *dev) sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3; sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; - printk_spew("sata_bar0=%x\n", sata_bar0); /* 3030 */ - printk_spew("sata_bar1=%x\n", sata_bar1); /* 3070 */ - printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ - printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ - printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */ + printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */ + printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */ + printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */ + printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */ + printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ + printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */ /* disable combined mode */ byte = pci_read_config8(sm_dev, 0xAD); @@ -199,12 +199,12 @@ static void sata_init(struct device *dev) for (i = 0; i < 4; i++) { byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk_spew("SATA port %i status = %x\n", i, byte); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; if( byte == 0x1 ) { /* If the drive status is 0x1 then we see it but we aren't talking to it. */ /* Try to do something about it. */ - printk_spew("SATA device detected but not talking. Trying lower speed.\n"); + printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); /* Read in Port-N Serial ATA Control Register */ byte = read8(sata_bar5 + 0x12C + 0x80 * i); @@ -225,7 +225,7 @@ static void sata_init(struct device *dev) /* Reread status */ byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk_spew("SATA port %i status = %x\n", i, byte); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; } @@ -234,13 +234,13 @@ static void sata_init(struct device *dev) if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2)) break; } - printk_debug("%s %s device is %sready after %i tries\n", + printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", (j == 10) ? "not " : "", (j == 10) ? j : j + 1); } else { - printk_debug("No %s %s SATA drive on Slot%i\n", + printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", i); } @@ -267,7 +267,7 @@ static void sata_init(struct device *dev) /* word = pm_ioread(0x28); */ /* byte = pm_ioread(0x29); */ /* word |= byte<<8; */ - /* printk_debug("AcpiGpe0Blk addr = %x\n", word); */ + /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */ /* write32(word, 0x80000000); */ } diff --git a/src/southbridge/amd/sb700/sb700_sm.c b/src/southbridge/amd/sb700/sb700_sm.c index dbd7a6ab02..d053aff0fd 100644 --- a/src/southbridge/amd/sb700/sb700_sm.c +++ b/src/southbridge/amd/sb700/sb700_sm.c @@ -54,7 +54,7 @@ static void sm_init(device_t dev) u32 on; u32 nmi_option; - printk_info("sm_init().\n"); + printk(BIOS_INFO, "sm_init().\n"); ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */ /* Don't rename APIC ID */ @@ -118,7 +118,7 @@ static void sm_init(device_t dev) } byte |= 1 << 2; pm_iowrite(0x74, byte); - printk_info("set power %s after power fail\n", on ? "on" : "off"); + printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); byte = pm_ioread(0x68); byte &= ~(1 << 1); @@ -152,10 +152,10 @@ static void sm_init(device_t dev) get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ - printk_info("++++++++++set NMI+++++\n"); + printk(BIOS_INFO, "++++++++++set NMI+++++\n"); } else { byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */ - printk_info("++++++++++no set NMI+++++\n"); + printk(BIOS_INFO, "++++++++++no set NMI+++++\n"); } byte &= ~(1 << 7); if (byte != byte_old) { @@ -217,7 +217,7 @@ static void sm_init(device_t dev) byte &= ~(1 << 1); pm_iowrite(0x59, byte); - printk_info("sm_init() end\n"); + printk(BIOS_INFO, "sm_init() end\n"); /* Enable NbSb virtual channel */ axcfg_reg(0x114, 0x3f << 1, 0 << 1); diff --git a/src/southbridge/amd/sb700/sb700_smbus.c b/src/southbridge/amd/sb700/sb700_smbus.c index 91bbea852d..7ba2a7d264 100644 --- a/src/southbridge/amd/sb700/sb700_smbus.c +++ b/src/southbridge/amd/sb700/sb700_smbus.c @@ -196,7 +196,7 @@ static void alink_ab_indx(u32 reg_space, u32 reg_addr, tmp &= ~mask; tmp |= val; - /* printk_debug("about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */ + /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */ outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl(tmp, AB_DATA); reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL; diff --git a/src/southbridge/amd/sb700/sb700_usb.c b/src/southbridge/amd/sb700/sb700_usb.c index 63679b8847..d2dcf852f2 100644 --- a/src/southbridge/amd/sb700/sb700_usb.c +++ b/src/southbridge/amd/sb700/sb700_usb.c @@ -82,7 +82,7 @@ static void usb_init2(struct device *dev) /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; - printk_info("usb2_bar0=0x%x\n", usb2_bar0); + printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0); /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; @@ -163,7 +163,7 @@ static void usb_init2(struct device *dev) dword |= 1 << 8; dword &= ~(1 << 27); /* 6.23 */ } - printk_debug("rpr 6.23, final dword=%x\n", dword); + printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword); #endif } |