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authorRonald G. Minnich <rminnich@gmail.com>2006-05-05 18:18:33 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-05-05 18:18:33 +0000
commit694d20e2d62f2193168f87377eaf245df80e5014 (patch)
treefa4143cebbaf1da8dd95a5ac752be393a5d31fa8 /src/southbridge/amd
parent1656c18d76773afe2b48dd8bf29d8f4e0b40d6ba (diff)
This is to enable COM1 early.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/cs5536/cs5536_early_setup.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c
index 710adccf7c..9f030c9710 100644
--- a/src/southbridge/amd/cs5536/cs5536_early_setup.c
+++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c
@@ -190,12 +190,13 @@ static int cs5536_setup_onchipuart(void)
msr_t msr;
msr.lo = 2;
msr.hi = 0;
- /* not sure what this is for, so comment it out ...
- wrmsr(0x5140003a, msr);
+ /* This enables COM2, but that should be done elsewhere
wrmsr(0x5140003e, msr);
*/
+ /* enable COM1 */
+ wrmsr(0x5140003a, msr);
/* GPIO8 - UART1_TX */
/* Set: Output Enable (0x4) */
m = inl(GPIOL_OUTPUT_ENABLE);