diff options
| author | Martin Roth <martinroth@google.com> | 2016-01-11 12:47:30 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-18 04:07:53 +0100 |
| commit | fd277d8f9406c746ed929a042e01afd31022b605 (patch) | |
| tree | 1c423c912a6afc6ff4373db2fc8fde2009238570 /src/southbridge/amd | |
| parent | a656362402ae50a767fcff091087df3946ebc7af (diff) | |
header files: Fix guard name comments to match guard names
This just updates existing guard name comments on the header files
to match the actual #define name.
As a side effect, if there was no newline at the end of these files,
one was added.
Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/cimx/sb700/Platform.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5535/chip.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs690/rs690.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/rs780/rs780.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/sr5650.h | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h index 45dda17425..7562417dd7 100644 --- a/src/southbridge/amd/cimx/sb700/Platform.h +++ b/src/southbridge/amd/cimx/sb700/Platform.h @@ -82,4 +82,4 @@ void TraceCode ( UINT32 Level, UINT32 Code); #define DMSG_SB_TRACE 0x02 -#endif //#ifndef _AMD_SB_CIMx_PLATFORM_H_ +#endif /* _AMD_SB_CIMx_PLATFORM_H_ */ diff --git a/src/southbridge/amd/cs5535/chip.h b/src/southbridge/amd/cs5535/chip.h index d4dde3d6ee..37e5eadddd 100644 --- a/src/southbridge/amd/cs5535/chip.h +++ b/src/southbridge/amd/cs5535/chip.h @@ -5,4 +5,4 @@ struct southbridge_amd_cs5535_config { int setupflash; }; -#endif /* _SOUTHBRIDGE_AMD_CS5536 */ +#endif /* _SOUTHBRIDGE_AMD_CS5535 */ diff --git a/src/southbridge/amd/rs690/rs690.h b/src/southbridge/amd/rs690/rs690.h index c0f13ac06f..9a2fec5196 100644 --- a/src/southbridge/amd/rs690/rs690.h +++ b/src/southbridge/amd/rs690/rs690.h @@ -134,4 +134,4 @@ void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev); void config_gpp_core(device_t nb_dev, device_t sb_dev); void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); -#endif /* RS690_H */ +#endif /* __RS690_H__ */ diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index 341de0d487..ffd0e15172 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -210,4 +210,4 @@ int cpuidFamily(void); int is_family0Fh(void); int is_family10h(void); void pcie_hide_unused_ports(device_t nb_dev); -#endif /* RS780_H */ +#endif /* __RS780_H__ */ diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h index c6db26da5a..ea7005c9ef 100644 --- a/src/southbridge/amd/sr5650/sr5650.h +++ b/src/southbridge/amd/sr5650/sr5650.h @@ -132,4 +132,4 @@ void sr5650_nb_pci_table(device_t nb_dev); void init_gen2(device_t nb_dev, device_t dev, u8 port); void sr56x0_lock_hwinitreg(void); struct resource * sr5650_retrieve_cpu_mmio_resource(void); -#endif /* SR5650_H */ +#endif /* __SR5650_H__ */ |