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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-19 16:22:53 -0500 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-21 21:32:51 +0200 |
| commit | cf38facbd2255562cfbf2a2bc528794fafa5891a (patch) | |
| tree | b956c46eb5182c602d184693b17f6561f7283cae /src/southbridge/amd | |
| parent | 7efd5fda490dba79a30aeb83d966349eaf59baea (diff) | |
hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18
The PCIE PME pin from the APU is connected to GEVENT8, but the
northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map
accordingly.
Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5556
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
0 files changed, 0 insertions, 0 deletions