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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-21 21:29:16 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-04 12:17:52 +0000 |
| commit | 98a917443efa7429dd92b073e00876cfb274a058 (patch) | |
| tree | 00f0b56191323e4e41d987707c303c409c051eac /src/southbridge/amd | |
| parent | ad7674ed00a810b472b2f66b3f5b2e0edbea02de (diff) | |
device: Replace ugly cases of dev_find_slot()
These few cases lacked a proper devfn parameter in the
form of PCI_DEVFN(dev, fn).
Change-Id: Iad0b214df12dee65360d07e887a960b0c73a3e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/rs780/gfx.c | 10 | ||||
| -rw-r--r-- | src/southbridge/amd/sr5650/pcie.c | 4 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index b17aebb0cc..575a340894 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -319,9 +319,9 @@ static void internal_gfx_pci_dev_init(struct device *dev) u16 command; u32 value; u16 deviceid, vendorid; - struct device *nb_dev = dev_find_slot(0, 0); - struct device *k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); - struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + struct device *nb_dev = pcidev_on_root(0x0, 0); + struct device *k8_f2 = pcidev_on_root(0x18, 2); + struct device *k8_f0 = pcidev_on_root(0x18, 0); static const u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32}; static const u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0}; static const u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200}; @@ -733,7 +733,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) static void rs780_internal_gfx_disable(struct device *dev) { u32 l_dword; - struct device *nb_dev = dev_find_slot(0, 0); + struct device *nb_dev = pcidev_on_root(0x0, 0); /* Disable internal GFX and enable external GFX. */ l_dword = pci_read_config32(nb_dev, 0x8c); @@ -753,7 +753,7 @@ static void rs780_internal_gfx_enable(struct device *dev) { u32 l_dword; int i; - struct device *nb_dev = dev_find_slot(0, 0); + struct device *nb_dev = pcidev_on_root(0x0, 0); msr_t sysmem; #if !IS_ENABLED(CONFIG_GFXUMA) diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index f2fd5392fc..5084a122ce 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -447,8 +447,8 @@ static void EnableLclkGating(struct device *dev) u32 reg = 0; u32 mask = 0; u32 value = 0; - struct device *nb_dev = dev_find_slot(0, 0); - struct device *clk_f1= dev_find_slot(0, 1); + struct device *nb_dev = pcidev_on_root(0x0, 0); + struct device *clk_f1 = pcidev_on_root(0x0, 1); reg = 0xE8; port = dev->path.pci.devfn >> 3; |