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authorStefan Reinauer <stefan.reinauer@coreboot.org>2011-06-04 10:36:21 -0700
committerCristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>2011-06-07 11:58:31 +0200
commit44c1d3111b4c0873ddb459ba832cdfcb20a7437a (patch)
treefbcec4644ddf2ebbd338dade2045dfffbe40c54d /src/southbridge/amd
parentc21b054acc866dc79c4783338e97337b9ca9c587 (diff)
re-indent, so files conform to coding guidelines.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab Reviewed-on: http://review.coreboot.org/8 Tested-by: build bot (Jenkins) Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/cimx_wrapper/sb800/bootblock.c63
1 files changed, 31 insertions, 32 deletions
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
index 629685d689..9d8a349c6e 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
@@ -17,48 +17,47 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include <arch/io.h>
#include <arch/romcc_io.h>
static void sb800_enable_rom(void)
{
- u32 word;
- u32 dword;
- device_t dev;
+ u32 word;
+ u32 dword;
+ device_t dev;
- dev = PCI_DEV(0, 0x14, 0x03);
- /* SB800 LPC Bridge 0:20:3:44h.
- * BIT6: Port Enable for serial port 0x3f8-0x3ff
- * BIT29: Port Enable for KBC port 0x60 and 0x64
- * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
- */
- dword = pci_io_read_config32(dev, 0x44);
- //dword |= (1<<6) | (1<<29) | (1<<30) ;
- /* Turn on all of LPC IO Port decode enable */
- dword = 0xffffffff;
- pci_io_write_config32(dev, 0x44, dword);
+ dev = PCI_DEV(0, 0x14, 0x03);
+ /* SB800 LPC Bridge 0:20:3:44h.
+ * BIT6: Port Enable for serial port 0x3f8-0x3ff
+ * BIT29: Port Enable for KBC port 0x60 and 0x64
+ * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
+ */
+ dword = pci_io_read_config32(dev, 0x44);
+ //dword |= (1<<6) | (1<<29) | (1<<30) ;
+ /* Turn on all of LPC IO Port decode enable */
+ dword = 0xffffffff;
+ pci_io_write_config32(dev, 0x44, dword);
- /* SB800 LPC Bridge 0:20:3:48h.
- * BIT0: Port Enable for SuperIO 0x2E-0x2F
- * BIT1: Port Enable for SuperIO 0x4E-0x4F
- * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
- * BIT6: Port Enable for RTC IO 0x70-0x73
- * BIT21: Port Enable for Port 0x80
- */
- dword = pci_io_read_config32(dev, 0x48);
- dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
- pci_io_write_config32(dev, 0x48, dword);
+ /* SB800 LPC Bridge 0:20:3:48h.
+ * BIT0: Port Enable for SuperIO 0x2E-0x2F
+ * BIT1: Port Enable for SuperIO 0x4E-0x4F
+ * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
+ * BIT6: Port Enable for RTC IO 0x70-0x73
+ * BIT21: Port Enable for Port 0x80
+ */
+ dword = pci_io_read_config32(dev, 0x48);
+ dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
+ pci_io_write_config32(dev, 0x48, dword);
- /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
- /* Set the 4MB enable bits */
- word = pci_io_read_config16(dev, 0x6c);
- word = 0xFFC0;
- pci_io_write_config16(dev, 0x6c, word);
+ /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+ /* Set the 4MB enable bits */
+ word = pci_io_read_config16(dev, 0x6c);
+ word = 0xFFC0;
+ pci_io_write_config16(dev, 0x6c, word);
}
static void bootblock_southbridge_init(void)
{
- /* Setup the rom access for 2M */
- sb800_enable_rom();
+ /* Setup the rom access for 2M */
+ sb800_enable_rom();
}