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authorStefan Reinauer <reinauer@chromium.org>2013-03-21 11:51:41 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-22 00:00:09 +0100
commit24d1d4b47274eb82893e6726472a991a36fce0aa (patch)
tree57126316330f6f9d407f605fa831ce530650f069 /src/southbridge/amd
parent55ed3106556a9bcbe36d3389dc5230d4a4ee2a40 (diff)
x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/agesa/hudson/bootblock.c1
-rw-r--r--src/southbridge/amd/agesa/hudson/early_setup.c3
-rw-r--r--src/southbridge/amd/agesa/hudson/enable_usbdebug.c1
-rw-r--r--src/southbridge/amd/agesa/hudson/reset.c8
-rw-r--r--src/southbridge/amd/amd8111/bootblock.c1
-rw-r--r--src/southbridge/amd/cimx/sb700/bootblock.c2
-rw-r--r--src/southbridge/amd/cimx/sb700/early.c6
-rw-r--r--src/southbridge/amd/cimx/sb800/bootblock.c1
-rw-r--r--src/southbridge/amd/cimx/sb800/early.c4
-rw-r--r--src/southbridge/amd/cimx/sb900/bootblock.c3
-rw-r--r--src/southbridge/amd/cimx/sb900/early.c43
-rw-r--r--src/southbridge/amd/sb600/bootblock.c1
-rw-r--r--src/southbridge/amd/sb600/enable_usbdebug.c1
-rw-r--r--src/southbridge/amd/sb600/reset.c6
-rw-r--r--src/southbridge/amd/sb700/bootblock.c1
-rw-r--r--src/southbridge/amd/sb700/early_setup.c2
-rw-r--r--src/southbridge/amd/sb700/enable_usbdebug.c1
-rw-r--r--src/southbridge/amd/sb700/reset.c8
-rw-r--r--src/southbridge/amd/sb800/bootblock.c1
-rw-r--r--src/southbridge/amd/sb800/enable_usbdebug.c1
-rw-r--r--src/southbridge/amd/sb800/reset.c8
-rw-r--r--src/southbridge/amd/sr5650/early_setup.c1
22 files changed, 41 insertions, 63 deletions
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index 23be162507..65810facf3 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -19,7 +19,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <device/pci_ids.h>
/*
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index 00ca7c67cc..a0319abdf9 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -21,8 +21,7 @@
#define _HUDSON_EARLY_SETUP_C_
#include <stdint.h>
-#include <arch/io.h> /* inl, outl */
-#include <arch/romcc_io.h> /* device_t */
+#include <arch/io.h>
#include <arch/acpi.h>
#include <console/console.h>
#include <reset.h>
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index e1e885c4a1..c74ac9ac61 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -18,7 +18,6 @@
*/
#include <stdint.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <usbdebug.h>
#include <device/pci_def.h>
#include "hudson.h"
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index c48aaeb9af..315a065380 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -17,11 +17,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <reset.h>
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
#include <arch/io.h>
-#include <arch/romcc_io.h>
+#include <reset.h>
-#include "../../../northbridge/amd/amdk8/reset_test.c"
+#include <northbridge/amd/amdk8/reset_test.c>
void hard_reset(void)
{
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
index 2df1fb9f07..ba3dc431a0 100644
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ b/src/southbridge/amd/amd8111/bootblock.c
@@ -20,7 +20,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <device/pci_ids.h>
/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 8d77d22ce3..fc7f3c52cc 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -19,8 +19,6 @@
#include <arch/io.h>
-#include <arch/romcc_io.h>
-
#if CONFIG_CONSOLE_POST
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index d9ce75aed3..13c6379def 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -17,12 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
-//#include <config.h>
#include <stdint.h>
#include <device/pci_ids.h>
-#include <arch/io.h> /* inl, outl */
-#include <arch/romcc_io.h> /* device_t */
+#include <arch/io.h>
#include "Platform.h"
#include "sb_cimx.h"
#include "sb700_cfg.h" /*sb700_cimx_config*/
@@ -30,7 +27,6 @@
#include <console/loglevel.h>
#include "smbus.h"
-
#if CONFIG_RAMINIT_SYSINFO
/**
* @brief Get SouthBridge device number
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index d21b4fdbfd..ac9351e4c2 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -18,7 +18,6 @@
*/
#include <arch/io.h>
-#include <arch/romcc_io.h>
static void enable_rom(void)
{
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 33afdcfe7a..83087f5527 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -17,19 +17,15 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
-//#include <config.h>
#include <stdint.h>
#include <device/pci_ids.h>
#include <arch/io.h> /* inl, outl */
-#include <arch/romcc_io.h> /* device_t */
#include <arch/acpi.h>
#include "SBPLATFORM.h"
#include "sb_cimx.h"
#include "cfg.h" /*sb800_cimx_config*/
#include "cbmem.h"
-
#if CONFIG_RAMINIT_SYSINFO
/**
* @brief Get SouthBridge device number
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index c88a9fa38c..106f664738 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -17,10 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include <arch/io.h>
-#include <arch/romcc_io.h>
-
#if CONFIG_CONSOLE_POST
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index 5acbfa03fe..d6036ddd19 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -17,19 +17,18 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
-//#include <config.h>
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
#include <stdint.h>
#include <device/pci_ids.h>
-#include <arch/io.h> /* inl, outl */
-#include <arch/romcc_io.h> /* device_t */
+#include <arch/io.h>
#include "SbPlatform.h"
#include "SbEarly.h"
#include <console/console.h>
#include <console/loglevel.h>
#include "smbus.h"
-
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
@@ -39,13 +38,13 @@ u32 get_sbdn(u32 bus)
{
device_t dev;
- printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - Start.\n");
- //dev = PCI_DEV(bus, 0x14, 0);
- dev = pci_locate_device_on_bus(
- PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB900_SM),
- bus);
+ printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - Start.\n");
+
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_ATI_SB900_SM), bus);
+
+ printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - End.\n");
- printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - End.\n");
return (dev >> 15) & 0x1f;
}
@@ -59,7 +58,7 @@ void sb_poweron_init(void)
AMDSBCFG sb_early_cfg;
u8 data;
- printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - Start.\n");
+ printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - Start.\n");
//Enable/Disable PCI Bridge Device 14 Function 4.
outb(0xEA, 0xCD6);
@@ -77,7 +76,7 @@ void sb_poweron_init(void)
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image.
sbPowerOnInit(&sb_early_cfg);
- printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - End.\n");
+ printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - End.\n");
}
/**
@@ -88,7 +87,7 @@ void sb_before_pci_init(void)
{
AMDSBCFG sb_early_cfg;
- printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - Start.\n");
+ printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - Start.\n");
sb900_cimx_config(&sb_early_cfg);
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
//AmdSbDispatcher(&sb_early_cfg);
@@ -96,14 +95,14 @@ void sb_before_pci_init(void)
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image.
sbBeforePciInit(&sb_early_cfg);
- printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - End.\n");
+ printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - End.\n");
}
void sb_After_Pci_Init(void)
{
AMDSBCFG sb_early_cfg;
- printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - Start.\n");
+ printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n");
sb900_cimx_config(&sb_early_cfg);
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
//AmdSbDispatcher(&sb_early_cfg);
@@ -111,14 +110,14 @@ void sb_After_Pci_Init(void)
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image.
sbAfterPciInit(&sb_early_cfg);
- printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - End.\n");
+ printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n");
}
void sb_Mid_Post_Init(void)
{
AMDSBCFG sb_early_cfg;
- printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n");
+ printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n");
sb900_cimx_config(&sb_early_cfg);
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
//AmdSbDispatcher(&sb_early_cfg);
@@ -126,7 +125,7 @@ void sb_Mid_Post_Init(void)
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image.
sbMidPostInit(&sb_early_cfg);
- printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - End.\n");
+ printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - End.\n");
}
void sb_Late_Post(void)
@@ -134,7 +133,7 @@ void sb_Late_Post(void)
AMDSBCFG sb_early_cfg;
u8 data;
- printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - Start.\n");
+ printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - Start.\n");
sb900_cimx_config(&sb_early_cfg);
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
//AmdSbDispatcher(&sb_early_cfg);
@@ -160,7 +159,5 @@ void sb_Late_Post(void)
outb(data, 0x4D0);
}
- printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - End.\n");
+ printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - End.\n");
}
-
-
diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c
index e848189df1..e31a96c8e3 100644
--- a/src/southbridge/amd/sb600/bootblock.c
+++ b/src/southbridge/amd/sb600/bootblock.c
@@ -19,7 +19,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <device/pci_ids.h>
/*
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index 4130dd5545..305362f37d 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -19,7 +19,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <usbdebug.h>
#include <device/pci_def.h>
#include "sb600.h"
diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c
index 0c94136992..0936516c4d 100644
--- a/src/southbridge/amd/sb600/reset.c
+++ b/src/southbridge/amd/sb600/reset.c
@@ -17,11 +17,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <reset.h>
-#include "northbridge/amd/amdk8/reset_test.c"
+#include <northbridge/amd/amdk8/reset_test.c>
void hard_reset(void)
{
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index cffa5ca1da..c290806911 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -19,7 +19,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <device/pci_ids.h>
/*
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index bc6f9107d0..a16fc9f2b2 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -23,7 +23,6 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
@@ -33,7 +32,6 @@
#include "sb700.h"
#include "smbus.h"
-
static void pmio_write(u8 reg, u8 value)
{
outb(reg, PM_INDEX);
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index a816253439..2a7fc383e4 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -20,7 +20,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <usbdebug.h>
#include <device/pci_def.h>
#include "sb700.h"
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index 9203b2bede..ef4115ecbe 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -17,9 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <reset.h> /* hard_reset, soft_rest*/
-#include <arch/io.h> /* inb, outb */
-#include <arch/romcc_io.h> /* pci_read_config32, device_t, PCI_DEV */
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
+#include <reset.h>
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5)
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index 9d90a34ce0..9311b978f9 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -19,7 +19,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <device/pci_ids.h>
/*
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index bdb4bde23c..f085eabecb 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -18,7 +18,6 @@
*/
#include <stdint.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <usbdebug.h>
#include <device/pci_def.h>
#include "sb800.h"
diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c
index c48aaeb9af..315a065380 100644
--- a/src/southbridge/amd/sb800/reset.c
+++ b/src/southbridge/amd/sb800/reset.c
@@ -17,11 +17,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <reset.h>
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
#include <arch/io.h>
-#include <arch/romcc_io.h>
+#include <reset.h>
-#include "../../../northbridge/amd/amdk8/reset_test.c"
+#include <northbridge/amd/amdk8/reset_test.c>
void hard_reset(void)
{
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index cc73cec54f..65bce13cf1 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -20,7 +20,6 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include "sr5650.h"