diff options
| author | Martin Roth <martinroth@google.com> | 2015-12-10 08:19:27 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-16 00:56:08 +0100 |
| commit | 1e1c7ac3b4cb6d85eb602e04b0e4da8c042846c0 (patch) | |
| tree | bc65f4d19be2551d4fdc1456518891ce164963fc /src/southbridge/amd | |
| parent | 49bbfcd5d393b8c14b46e46f0b20f150e4930b3d (diff) | |
southbridge/amd/sb600: Update HPET base address with #define
The SB600 code had the base address of the HPET hardcoded throughout.
It looks like the plan was to have it be updated in ACPI if needed,
but this wasn't ever implemented. The variable names being used to
do this update were the same, causing an IASL warning. Because of
this, the operation to update the HPET address actually did nothing.
This was fine, because it didn't actually need to be updated.
- Replace all that code with a #define.
- Add and update some comments in the same area.
Fixes IASL warning:
dsdt.aml 1505: Store(HPBA, HPBA)
Warning 3023 - ^ Duplicate value in list (Source is the
same as Target)
Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12705
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/sb600/sb600.h | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/sm.c | 2 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h index 93671fa516..5c1111adc4 100644 --- a/src/southbridge/amd/sb600/sb600.h +++ b/src/southbridge/amd/sb600/sb600.h @@ -16,8 +16,10 @@ #ifndef SB600_H #define SB600_H +#ifndef __ACPI__ #include <device/pci_ids.h> #include "chip.h" +#endif /* Power management index/data registers */ #define PM_INDEX 0xcd6 @@ -25,6 +27,9 @@ #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 +#define HPET_BASE_ADDRESS 0xfed00000 + +#ifndef __ACPI__ extern void pm_iowrite(u8 reg, u8 value); extern u8 pm_ioread(u8 reg); extern void pm2_iowrite(u8 reg, u8 value); @@ -36,4 +41,5 @@ void sb600_enable(device_t dev); void sb600_lpc_port80(void); void sb600_pci_port80(void); +#endif /* __ACPI__ */ #endif /* SB600_H */ diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c index 8cfd358b36..5773ae272a 100644 --- a/src/southbridge/amd/sb600/sm.c +++ b/src/southbridge/amd/sb600/sm.c @@ -305,7 +305,7 @@ static void sb600_sm_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; res = new_resource(dev, 0x14); /* hpet */ - res->base = 0xfed00000; /* reset hpet to widely accepted address */ + res->base = HPET_BASE_ADDRESS; /* reset hpet to widely accepted address */ res->size = 0x400; res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ res->align = 8; |